Flash memory device capable of reducing test time and test...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S189110, C365S230060, C365S238500

Reexamination Certificate

active

07099211

ABSTRACT:
A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.

REFERENCES:
patent: 5654925 (1997-08-01), Koh et al.
patent: 5793685 (1998-08-01), Suma
patent: 5805523 (1998-09-01), Lysinger
patent: 6236594 (2001-05-01), Kwon
patent: 6639854 (2003-10-01), Hur et al.
patent: 04-163798 (1992-06-01), None
patent: 2002-58992 (2002-07-01), None
English Language of Abstract of Korean Patent Publication No. 2002-58992.
English Language of Abstract of Japanese Patent Publication No. 04-163798.

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