Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-27
2004-03-30
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C438S260000, C438S262000, C438S266000
Reexamination Certificate
active
06713336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flash memory devices and, more particularly, to a flash memory device and fabrication method therefor having improved gate capacitive coupling ratio between the floating and control gates.
2. Description of the Related Art
A flash memory device is manufactured by taking advantage of EPROM, having programming and erasing properties, and EEPROM which has electrically ensuring programming and erasing properties.
Flash memory devices realize one bit memory with one transistor and electrically perform programming and erasing. The programming and erasing are performed using a combined power supply of 12V/5V and particularly, programming is performed using hot electron by external high voltage and erasing is performed using F-N (Fowler-Nordheim) tunneling.
The structure and fabrication method of a conventional flash memory device will be described in more detail with reference to the accompanying drawings.
FIG. 1
is a top view of a conventional flash memory device and
FIGS. 2 and 3
are cross sectional views taken along the line A-A′ and the line B-B′ of
FIG. 1
, respectively. As shown, the conventional flash memory device includes a substrate
1
, an isolation layer
2
, a tunnel oxide layer
3
, a floating gate
4
, an ONO layer
5
, a control gate
6
, a polysilicon layer
6
a
, a tungsten silicide layer
6
b
, a TEOS oxide layer
6
c
, a nitride layer
6
d
and an anti-reflective coating layer
6
e.
Referring to
FIGS. 1
to
3
, control gates
6
having line form are arranged separately on the substrate
1
, wherein each control gate has a structure in which the polysilicon layer
6
a
, tungsten silicide layer
6
b
, TEOS oxide layer
6
c
, nitride layer
6
d
and anti-reflective coating layer
6
e
are stacked. A source region
8
and a drain region
9
are formed at both sides of the control gate
6
in the substrate
1
. A floating gate
4
is formed on an active region defined by an isolation layer
2
below the control gate
6
, with a tunnel oxide layer
3
being interposed.
The fabrication method of a conventional flash memory device will now be described in the following.
Trench type isolation layers are formed in a predetermined position of a semiconductor substrate by Shallow Trench Isolation (STI) process. A thin tunnel oxide layer and a first polysilicon layer are sequentially formed on the surface of the substrate, and then patterned in a line form extending in one direction on the active region of the substrate defined by the isolation layers.
An ONO layer, a second polysilicon layer, a tungsten silicide layer, a TEOS oxide layer, a nitride layer and an anti-reflective coating layer are sequentially deposited on the resulting structure, and then a control gate of line form is obtained by patterning the layers to be at right angles to the patterned first polysilicon layer
Self Align Etch (SAE) process is performed to remove the ONO layer, the first polysilicon layer and the tunnel oxide layer formed on the source/drain predetermined region, thereby obtaining a floating gate. Then, source and drain regions are formed in the active region at both sides of the control gate and succeeding processes including a metal wiring process are performed.
In the conventional flash memory device, the contact area between the floating gate and the control gate is small, since the floating gate and the control gate are arranged in a simple stack structure. Therefore, there is a limitation in the prior art as to the ability to increase cell gate capacitive coupling ratio and improve programming and erasing properties.
FIGS. 4 and 5
illustrate gate capacitive coupling ratio in a flash memory device. In the drawings, Vcg indicates control gate voltage, Vf indicates floating gate voltage, Vb indicates substrate voltage, Vs indicates source voltage, Cipo indicates floating gate-control gate capacitance, Cgb indicates gate-substrate capacitance, Cgd indicates gate-drain capacitance and Cgs indicates gate-source capacitance.
According to
FIGS. 4 and 5
, when Vd is 0, Vf is calculated as shown in formula {circle around (1)}.
Vf
=
Cipo
Cipo
+
Cgs
+
Cgd
+
Cgb
×
Vcg
1
◯
When Vcg is 0, Vf is calculated as shown in formula {circle around (2)}.
Vf
=
Cgd
Cipo
+
Cgs
+
Cgd
+
Cgb
×
Vd
2
◯
And, Vf is obtained by the sum of {circle around (1)} and {circle around (2)} according to the principle of superposition as shown in formula {circle around (3)}.
Vf
=
Cipo
Cipo
+
Cgs
+
Cgd
+
Cgb
×
Vcg
+
Cgd
Cipo
+
Cgs
+
Cgd
+
Cgb
×
Vd
3
◯
In the formulas, if the Cipo is increased the Vf is also increased accordingly. The Cipo is calculated as shown in formula {circle around (4)}.
C
=
A
L
4
◯
(A: Area, L: Length)
As a result, in the formula {circle around (3)}, if the contact area of the floating gate and control gate is increased, Vf is increased accordingly.
However, the conventional gate structure has a limited capacity for increasing the contact area and improving gate capacitive coupling ratio, due to the fact that the floating gate and the control gate are arranged in a simple stack structure.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and one object of the present invention is to provide a flash memory device having an increased contact area between the floating gate and control gate and a fabrication method therefor.
Another object of the present invention is to provide a flash memory device having improved programming and erasing properties by improving gate capacitive coupling ratio and a fabrication method therefor.
In order to accomplish the above objects, the present invention comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and for exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
The present invention further includes a fabrication method for a flash memory device comprising the steps of forming a first trench having a width including an active region and an isolation region at both sides thereof on a predetermined position of a semiconductor substrate; filling up a sacrificial layer in the first trench; patterning the sacrificial layer to expose the isolation regions of the first trench; forming a source region and a drain region by implanting impurity ions of a predetermined conductive type into the exposed first trench region; forming an isolation layer by filling up an insulating layer in the exposed first trench region; removing the patterned sacrificial layer to form a second trench exposing the active region; forming a tunnel oxide layer and a floating gate sequentially on the surface of the second trench; forming a control gate with a gate insulating layer interposed on the floating gate and the substrate; and forming metal wirings to be in contact with the source and the drain regions, respectively, through the isolation layer on the substrate.
The above objects and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.
REFERENCES:
patent: 5495441 (1996-02-01), Hong
patent: 5680345 (1997-10-01), Hsu et al.
patent: 5751038 (1998-05-01), Mukherjee
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5973356 (1999-10-01), Noble et al.
patent: 6002151 (1999-12-01),
Eom Jae Doo
Shin Sung Hun
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Lee Eddie
Vu Quang
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