Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-12-12
1998-12-01
Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257316, 257506, 257509, 257510, 257513, 257519, H01L 2900
Patent
active
058442707
ABSTRACT:
A highly integrated flash memory device having a stable cell is provided. The device includes a semiconductor substrate of a first conductive type; a field insulating layer buried in a first trench formed in the semiconductor substrate in order to define an active region; a tunnel insulating film formed on the active region; a first conductive layer for a floating gate formed on the tunnel insulating film; spacers formed on both the tunnel insulating film and the sidewalls of the first conductive layer; a buried insulating layer buried in a second trench formed by etching the substrate adjacent to the spacers; a buried junction layer contacting a lower portion and sidewalls of the buried insulating layer, and acting as a source and drain region including impurities of a second conductive type; a second conductive layer formed on the first conductive layer and connected to the first conductive layer to be used as a floating gate; an insulating layer formed on the second conductive layer; and a third conductive layer for a control gate formed on the insulating layer. Accordingly, the flash memory device has a cell capable of maintaining stable operation and is appropriate for high-integration.
REFERENCES:
patent: 5610419 (1997-03-01), Tanaka
patent: 5610420 (1997-03-01), Kuroda et al.
S. Tam et al., A High Density CMOS 1-T Electrically Erasable Non-Volatile (Flash) Memory Technology, VLSI Technology, 1988, IV-4, pp. 31-32.
Gautam Verma et al., Reliability Performance of ETOX Based Flash Memories, 1988 IEEE/IRPS, pp. 158-166.
Shin-ichi Kobayashi et al., Memory Array Architecture and Decoding Scheme For 3V Only Sector Erasable DINOR Flash Memory, VLSI Circuits, 1993, pp. 97-98.
"A High Capacitive-Coupling Ratio (HiCR) Cell For 3V-only 64 Mbit And Future Flash Memories" by Yosiaki S. Hisamune, Kohji Kanamori, Taishi Kubota, Yoshiyuki Suzuki Masaru Tsukji, Eiji Hasegawa, Akihiko Ishitani, and Takeshi Okazawa. 1993 IEEE--IEDM, pp. 19-22.
"A 0.4-um2 Self-Aligned Contactless Memory Cell Technology Suitable For 256-Mbit Flash Memories", by Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Akihiko Sato, Takashi Kobayashi, Yoshimi Sudo, Tada Morimoto, Hitoshi Kume, Takashi Nishida and Katsutaka Kimura. IEDM 94, pp. 921-923.
"A 1.28um2 Contactless Memory Cell Technology For A 3V-Only 64Mbit EEPROM". Hitoshi Kume, Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Tsutomu Okazaki, Naoki Miyamoto, Shun-ichi Saeki, Yuzuru Ohji, Masahiro Ushiyama, Jiro Yugami, Tasao Morimoto, and Takashi Nishida, IEDM 92, pp. 991-993.
"Memory Array Architecture And Decoding Scheme For 3 V Only Sector Erasable DINOR Flash Memory", by Shin-ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada. 1994 IEEE Journal of Solid-State Circuits, vol. 29, No. 4, pp. 454-457.
"A Single Transistor EEPROM Cell And Its Implementation In a 512K CMOS EEPROM", by Satyen Mukherjee, Thomas Chang, Richard Pang, Mark Knecht and Dan Hu. IEDM 85, pp. 616-619.
"A Novel Cell Structure Suitable For A 3 Volt Operation, Sector Erase Flash Memory", by H. Onoda, Y. Kunori, S. Kobayashi, M. Ohi, A Fukumoto, N. Ajika and H. Miyoshi. 1992 IEDM, pp. 599-602.
International Electron Devices Meeting, Washington, D.C., Dec. 10-13, 1995; Session 11. "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable To The 256 Mbit and 1 Gbit Flash Memories" by K.S. Kim, J.Y. Kim, J.W. Yoo, Y.B. Choi, M.K. Kim, B.Y. Nam, K.T. Park, S.T. Ahn, and O.H. Kwon, pp. 263-266.
Choi Yong-bae
Kim Keon-soo
Yoo Jong-weon
Samsung Electronics Co,. Ltd.
Wallace Valencia
LandOfFree
Flash memory device and manufacturing method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory device and manufacturing method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory device and manufacturing method therefor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2397639