Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-09-12
2008-12-16
Rinehart, Mark (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S074000, C710S305000
Reexamination Certificate
active
07467251
ABSTRACT:
A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i−l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i−1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.
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Lee Jin-Wook
Park Min-Gun
Cleary Thomas J.
Mills & Onello LLP
Rinehart Mark
Samsung Electronics Co,. Ltd.
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