Flash memory cell with self-aligned gates and fabrication...

Details Flash memory cell with self-aligned gates and fabrication... Flash memory cell with self-aligned gates and fabrication...

1999-10-26

2001-09-18

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C438S596000

Reexamination Certificate

active

06291297

ABSTRACT:

This invention pertains generally to semiconductor devices and, more particularly, to a nonvolatile memory device with a self-aligned gates and to a process for fabricating the same.
Nonvolatile memory devices currently in use for retaining stored data during periods when no power is applied include PROM (programmable read only memory), EPROM (electrically programmable read only memory), EEPROM (electrically erasable programmable read only memory), and flash EEPROM devices.
EPROM, EEPROM and flash EEPROM devices have an advantage over PROM devices in that the data stored in them can be erased and rewritten. In EPROM devices, the data is erased by exposure to UV light, and in EEPROM and in flash EEPROM devices, it is erased electrically. Flash EEPROM devices differ from EEPROM devices in that the data can be erased in blocks ranging in size from 128 to 64K bytes, rather than on a byte-by-byte basis.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 1.0-2.0 volts after an erase cycle, which adds complexity to the circuit design.
Although a split-gate memory cell has no over erase problem, it generally includes an additional gate known as a select gate. Such cells are typically fabricated in double-poly or triple-poly processes which involve relatively complex processing steps. In addition, split-gate cells are generally larger than stack-gate cells. Nevertheless, because of the relatively simple circuit design which is possible when there is no over-erase problem, split-gate cells are used widely, particularly in embedded nonvolatile memory applications.
In the manufacture of split-gate memory cells, the floating gate pattern is commonly formed with one photolithographic mask, and the control gate or select gate pattern is then defined with another mask. Examples of this technique are found in U.S. Pat. Nos. 4,794,565, 5,029,130 and 5,455,792. During formation of the floating gate, corner rounding can occur, and the pattern can shift relative to the active area. Also, limitations in the accuracy and resolution of the photolithographic process can result in misalignment of the floating gate. Similarly, pattern shift of the control gate or select gate relative to the floating gate can also cause alignment problems. In a typical array in which two adjacent memory cells share the same drain or source region, the overall misalignment can cause one cell to have a very short channel length for the floating gate and/or the select gate. The short channel and punch through effects may make it difficult or impossible to identify the logic state of the cell clearly. These problems make process control more difficult, and may require the cell array layout to be larger in order to provide tolerance for process variations.
In the erase mode, electrons are forced to migrate away from the floating gate so that it becomes charged with positive ions. This is commonly accomplished by Fowler-Nordheim tunneling in which a tunnel oxide having a thickness on the order of 70-120 Å is formed between the monocrystalline silicon substrate and the floating gate. A relative strong electric field (greater than 10 mV/cm) is then applied to the tunnel oxide, and the electrons tunnel from the floating gate toward the underlying source, drain or channel region. This technique is widely used both in stack-gate cells and in split-gate cells, and is described in greater detail in U.S. Pat. Nos. 5,402,371, 5,284,784 and 5,445,792.
A prior art split-gate sidewall-type EEPROM memory cell
16
which utilizes Fowler-Nordheim tunneling is illustrated in FIG.
1
. This cell has a silicon substrate
17
, with source and drain regions
18
,
19
formed in a channel region
21
. A floating gate
22
and a control gate
23
are formed above the channel region, with a gate oxide
24
between the substrate and the floating gate, and a dielectric film
26
between the floating gate and the control gate. A select gate
27
is formed to one side of the floating gate and the control gate, with an oxide layer
28
between it and the substrate, and a dielectric film
29
between it and the other two gates.
In the program mode, control gate
23
is biased at a high positive voltage (e.g., 18 volts), and the source, drain and select gate are biased at 0 volts. This establishes a strong electric field across gate oxide
24
, which initiates Fowler-Nordheim tunneling, with electrons migrating from the channel region to the floating gate.
In the erase mode, a positive voltage of about9 volts is applied to channel region
21
, a negative voltage of about −9 volts is applied to the control gate, and the source, drain and select gate are left open. The strong negative electric field thus created across gate oxide
24
initiates Fowler-Nordheim tunneling, with electrons migrating from the floating gate
22
to the channel region beneath the floating gate.
Another popular technique for programming split-gate memory cells is hot carrier injection. This technique is illustrated in
FIG. 2
in connection with a split-gate flash EEPROM memory cell of the prior art. This cell differs from the cell of
FIG. 1
in that a portion of select gate
31
overhangs control gate
23
. The channel includes a region
21
a
beneath the select gate, a region
21
b
beneath the floating gate, and a mid-channel region
21
c
between the select gate and the floating gate.
In the program mode, control gate
23
is biased at a high voltage (e.g., 12 volts), select gate
31
and drain node
19
are biased at about 3 volts, and source node
18
is grounded. With this biasing, most of the drain-to-source voltage is applied to a mid-channel region
21
c
between the select gate and the floating gate, thereby establishing a high electric field in that region. As electrons flow from the source to the drain, some of them are accelerated by the electric field in the mid-channel region and become heated. The floating gate, which is coupled to the control gate, is at a higher voltage level than the voltage in the mid-channel region. This creates a vertical electric field between the floating gate and the channel region. Some of the hot electrons get accelerated by the vertical field, which causes them to overcome the energy barrier of the oxide and be injected into the floating gate.
In the erase mode, control gate
23
is biased at a negative voltage of about −12 volts, drain node
19
is biased at a voltage of about 3 volts, and select gate
31
and source node
18
are grounded. A high voltage is now established across the oxide layer
24
between floating gate
22
and the drain region under the floating gate. That causes electrons to tunnel from the floating gate to the drain region. This technique is disclosed in U.S. Pat. Nos. 5,284,784 and 5,445,792.
A prior art split-gate flash memory cell which has a floating gate
23
and a control gate
32
, but no select gate is illustrated in FIG.
3
. In this cell, a portion of the control gate crosses over or overhangs the floating gate, channel region
21
a
is located beneath the control gate, channel region
21
b
is located beneath the floating gate, and mid-channel region
21
c
is located between the control gate and the floating gate.
In the program mode, source
18
is biased at a high voltage (e.g., 12 volts), control gate
32
is biased at about 3 volts, and drain
19
is grounded. As in the cell of
FIG. 2
, hot electrons are generated in mid-channel region
21
c
and are injected into the floa

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