Flash memory cell transistor with threshold adjust implant...

Details Flash memory cell transistor with threshold adjust implant... Flash memory cell transistor with threshold adjust implant...

2007-12-07

2008-12-09

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S290000, C257S288000, C257SE21177, C257SE27066

Reexamination Certificate

active

07462543

ABSTRACT:
A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy and the first and second N-type regions form the source and drain regions of the NMOS transistor; forming a channel doped region by a second implantation process using the patterned photoresist as an implant mask where the second implantation process uses a low implant dose at a high implant energy and the channel doped region is formed for adjusting a threshold voltage of the NMOS transistor.

REFERENCES:
patent: 5877525 (1999-03-01), Ahn
patent: 6410394 (2002-06-01), Shao et al.
patent: 6949784 (2005-09-01), Moore
patent: 7268040 (2007-09-01), Shim

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