Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-12
2001-09-04
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S302000, C438S983000
Reexamination Certificate
active
06284603
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of fabricating a FLASH EEPROM device with improved channel punch-through characteristics.
(2) Description of the Prior Art
Flash EEPROM memories are widely used in the electronics industry. Many applications require the ability to change and retain data after removing the system power. Flash EEPROM offers this capability.
One type of Flash EEPROM cell is called a Fowler-Nordheim (FN) tunneling cell because electron injection across the tunneling oxide is described by the FN process. In an FN Flash EEPROM, a large gate to drain overlap is required to create sufficient electron injection efficiency. This means that a relatively deep drain junction is formed.
As the Flash EEPROM cell size is reduced, however, the distance between the deep drain junction and the source junction is reduced. The voltage at which punch-through between drain and source occurs is likewise reduced. If the punch-through voltage is too low, the cell is not useful in a circuit.
To eliminate the punch-through problem for the short channel Flash EEPROM, a threshold implant is performed. Referring now to
FIG. 1
, a partially completed prior art Flash EEPROM cell is shown. Isolation regions
14
are formed in the semiconductor substrate
10
to define the active area for the device. An implanting oxide
18
has been formed overlying the semiconductor substrate
10
. Ions are implanted
22
into the semiconductor substrate
10
to form a threshold enhancement region
26
near the surface of the semiconductor substrate
10
. The threshold enhancement region
26
is of the same impurity or dopant type as the semiconductor substrate
10
. For example, if the semiconductor substrate
10
is p-type, then the threshold enhancement region
26
is also p-type. The threshold enhancement region
26
would have a higher p-type concentration than the semiconductor substrate
10
.
Referring now to
FIG. 2
, a gate stack is defined overlying the semiconductor substrate
10
. The gate stack comprises a tunneling oxide layer
30
, a floating gate
34
, an interpoly dielectric layer
38
, and a control gate
42
. A shallow source junction
50
is formed in the semiconductor substrate
10
. A drain junction
48
and
46
is formed in the semiconductor substrate
10
. The drain junction is typically formed much deeper that than source junction
50
to facilitate the FN tunneling effect. The drain junction may comprise a double-diffused structure where a deep drain
48
contains a shallow drain
46
. The drain junction
48
and
46
and the source junction
50
are formed of the opposite type to the semiconductor substrate
10
.
The presence of the threshold enhancement region
26
increases the voltage threshold of the device. This tends to increase the punch-through voltage as desired. Unfortunately, the increased threshold voltage can cause device performance problems. In addition, this is not a particularly efficient means of reducing the punch-through effect. The threshold may have to rise substantially before punch-through has been sufficiently reduced. Finally, the depth of the source junction
50
and the drain junction
48
and
46
can cause buried punch-through phenomenon that cannot be controlled by the presence of the near-surface threshold enhancement region
26
.
Several prior art approaches deal with Flash EEPROM devices. U.S. Pat. No. 5,891,774 to Ueda et al discloses a method to form nonvolatile memory cells with a high concentration impurity layer formed adjacent to the drain region. The high concentration impurity layer is formed by an oblique ion implantation. The spacing and height of the gate stack, combined with the implantation angle, masks the implantation from the source region. The oblique angle ion implantation of the drain region is performed to improve channel hot electron programming efficiency. U.S. Pat. No. 5,998,263 to Sekariapuram et al teaches a method to form compact nonvolatile cells in trenches. The floating gate is formed over the trench sidewalls. The source is formed at the bottom of the trench. The drain is formed at the top of the trench. A tilt-angle ion implantation may be used for the voltage threshold implant. U.S. Pat. No. 5,355,006 to Iguchi discloses a method to form a DRAM device. Narrowly-spaced source and drain regions are formed using a two-directional oblique angle ion implantation. The shadowing effect of the gates masks a part of the drain and source regions from the implantation. U.S. Pat. No. 5,190,887 to Tang et al teaches a method to form a nonvolatile memory cell. An angled ion implantation is used to form a doped region adjacent to the drain. The implantation angle is selected so that the device gate stack blocks implantation into the source region. U.S. Pat. No. 5,759,896 to Hsu discloses a method to form a Flash memory cell. The gate stack is etched through on the drain side while etched only to the tunnel oxide on the source side. The source and drain ion implantation therefore forms the drain aligned to the gate stack. The source is therefore formed offset from the gate stack. A subsequent angled ion implantation forms a lightly-doped source region, of same dopant type, adjacent to the source. U.S. Pat. No. 5,770,502 to Lee teaches a method to form a double-diffused drain (DDD) region in a FLASH memory cell. Two angled ion implantation steps are used to form the DDD. The first implant is performed prior to sidewall spacer formation. The second implant is performed after sidewall spacer formation. The gate stack is used to mask implantation into undesired areas. U.S. Pat. No. 5,783,457 to Hsu discloses a method to form Flash memory cells. A first angled ion implantation is used to form a lightly-doped source region. A second angled ion implantation is used to form a counter-doped region adjacent to the drain and underlying the gate. U.S. Pat. No. 5,147,811 to Sakagami teaches a method to form a nonvolatile cell. Implanted regions are formed in both the source and the drain regions. The implanted regions are formed by an angled ion implantation after the gate formation. The implantation is self-aligned to the gate and is not masked. However, such implantation of both source and drain regions will degrade the programming characteristics in the case of a Fowler-Nordheim tunneling cell.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a Flash EEPROM memory cell in the manufacture of an integrated circuit device.
A further object of the present invention is to provide a method of fabricating a Flash EEPROM memory cell with an increased drain to source punch-through voltage.
A yet further object of the present invention is to increase the drain to source punch-through voltage by containing the source junction in a channel stop junction of the same impurity type as the impurity type of the semiconductor substrate.
A still yet further object of the present invention is to form an opposite-type channel stop junction by ion implantation at a non-perpendicular angle.
Another further object of the present invention is to increase the drain to source punch-through voltage while eliminating the threshold voltage ion implantation.
In accordance with the objects of this invention, a new method of fabricating a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed overlying the semiconductor substrate. A first conductive layer is deposited overlying the tunneling oxide layer. An interpoly dielectric layer, which may comprise silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride, is deposited overlying the first conductive layer. A second conductive layer is deposited overlying the interpoly d
Ho Simon Chan Tze
Kim Sung Rae
Lin Yung-Tao
Stodart Tyrone Philip
Chartered Semiconductor Manufacturing Inc.
Lebentritt Michael S.
Pike Rosemary L.S.
Saile George O.
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