Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-02-15
2005-02-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C257S315000
Reexamination Certificate
active
06855598
ABSTRACT:
A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a plurality of first oxide layers formed aside each of the floating gates, a dielectric layer formed on each of the floating gates, a control gate formed on each of the dielectric layers, a plurality of second oxide layers formed on surfaces of the control gates and extending toward both sides of the control gates, a lateral width of each second oxide layer being larger than a lateral width of each oxide layer, a third oxide layer formed on the source, and an erasing gate formed on the third oxide layer and located between the floating gates.
REFERENCES:
patent: 6503785 (2003-01-01), Chen
patent: 20040057286 (2004-03-01), Chen et al.
patent: 20040065917 (2004-04-01), Fan et al.
Du Chien-Chih
Hsu Cheng-Yuan
Hung Chih-Wei
Sung Da
Le Thao P.
Nelms David
Powerchip Semiconductor Corp.
Winston Hsu
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