Flash memory cell having reduced floating gate to floating...

Details Flash memory cell having reduced floating gate to floating... Flash memory cell having reduced floating gate to floating...

2006-10-17

2008-12-16

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000, C438S257000, C438S692000, C257SE21170, C257SE21006, C257SE21165, C257SE21278, C257SE21293, C257SE21304, C257SE21645

Reexamination Certificate

active

07465625

ABSTRACT:
According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

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Office Action from U.S. Appl. No. 11/095,330 mailed Nov. 9, 2006, 6 pages.
Office Action from U.S. Appl. No. 11/095,330 mailed Mar. 27, 2007, 7 pages.
Office Action from U.S. Appl. No. 11/095,330 mailed Aug. 1, 2007, 7 pgs.

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