Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-11
2003-01-21
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06509237
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor processing. More specifically, the present invention relates to efficient methods of forming and controlling the configuration of source and drain junctions in transistor devices.
An example of a process of fabricating a transistor with a graded source junction, for increasing the source junction breakdown voltage and allowing higher voltages to be applied to the source of the transistor, is described in co-pending and commonly assigned U.S. patent application Ser. No. 09/777,007. In this fabrication process, the source junction is formed in a semiconductor substrate by masking the substrate for a source implant, implanting the source region with a dopant (or several dopants), removing the source mask, and activating and driving in the source dopant (i.e. diffusing the dopant) in the course of a thermo-cycle (i.e. diffusion cycle). Following these steps, a drain junction is then formed by masking the transistor for a drain implant, implanting the drain region with a dopant, removing the drain mask and, finally, activating and driving in the drain dopant.
During the diffusion cycles, the source and drain junctions spread laterally (and vertically) underneath the gate region of the transistor. While some degree of lateral diffusion is required to ensure that proper channel formation will result, excessive lateral diffusion presents limits as to how short the gate feature or gate length can be made. A limit is encountered due to the necessity of avoiding high leakage and punch-through, i.e., the merging of the source and drain depletion regions during operation. The inability to reduce the gate length is undesirable, since it prevents manufacturing smaller cell sizes and greater cell densities.
SUMMARY OF THE INVENTION
In a first aspect of the invention an abrupt drain junction and a graded source junction are fabricated using a common diffusion step. The common diffusion step is used to form both the drain and source junctions. This common diffusion process may be used in a NOR cell of a flash memory, but can also be used in other types of semiconductor transistors.
In a second aspect of the invention, a common diffusion step is performed after a dielectric spacer is formed over the transistor's gate stack.
In a third aspect of the invention, a transistor fabrication process starts with forming a gate structure on a substrate, according to conventional methods. After the gate structure has been formed, a drain region is covered by a source mask and a first source dopant is implanted in a source region of the substrate. An optional and additional dopant having a lower diffusivity, for example arsenic, may also be implanted during this step. In the next step the gate structure is covered with a dielectric material, such as, for example SiO
2
, to form a dielectric spacer. After the dielectric spacer is formed, a drain dopant, having a diffusivity that is lower than the diffusivity of the first source dopant (e.g. arsenic), is implanted in a drain region of the substrate. Finally, in the last step, the source and drain dopants are driven in by diffusion, to form source and drain junctions within the substrate.
In a fourth aspect of the invention, a transistor fabrication process starts with forming a gate stack on a semiconductor substrate, according to conventional methods. After the gate stack has been formed, a drain region of the transistor is covered by a source mask and a first dopant of, for example phosphorous, is implanted through the source mask, to form a source implant layer. An optional and additional dopant having a lower diffusivity, for example arsenic, may also be implanted during this step. In the next step, a dielectric layer is deposited and etched back to form a dielectric spacer over the gate stack. After the dielectric spacer is formed, another dopant having a lower diffusivity than the first dopant, for example arsenic, is implanted through a drain mask to form a drain implant layer. The source implant layer may be covered or uncovered during this step. Finally, both the source and drain regions are driven by diffusion to finalize formation of the source and drain junctions.
One advantage of the process is that, because of the presence of a source implant layer with higher diffusivity, e.g. phosphorus, diffusion is faster in the source region and results in a graded source junction, while the slower diffusion in the drain region results in a relatively more abrupt drain junction. Another advantage is that both the source and drain diffusions are performed at the same time, thereby simplifying and eliminating a step in the fabrication process.
An additional benefit is that the dielectric spacer moves the drain junction further away from the gates. This benefit occurs whether or not the cell is fabricated with the graded source/abrupt drain. With less of a drain-gate overlap, cells with the same effective channel length can be made with smaller gate feature sizes (or drawn channel lengths), thus allowing for greater cell density.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 4001050 (1977-01-01), Koo
patent: 5629220 (1997-05-01), Yang
patent: 5741736 (1998-04-01), Orlowski et al.
patent: 5763308 (1998-06-01), Choi
patent: 5920776 (1999-07-01), Fratin et al.
patent: 6232183 (2001-05-01), Chen et al.
Qian Frank
Rabkin Peter
Wang Hsingya Arthur
Blum David S
Chaudhuri Olik
Hynix Semiconductor America, Inc.
Townsend and Townsend / and Crew LLP
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