Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-25
2006-07-25
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000, C438S258000, C438S261000, C257S288000, C257S314000, C257S324000, C257S326000, C365S182000
Reexamination Certificate
active
07081381
ABSTRACT:
A process and product for making integrated circuits with dense logic and/or linear regions and dense memory regions is disclosed. On a common substrate, a dual hard mask process separately forms stacks of logic and/or linear transistors and EEPROM memory transistors. By using the process, the logic and/or linear and memory transistors are made with different sidewall insulating layers. The logic and/or linear transistors have relatively thin sidewall insulating layers sufficient to provide isolation from adjacent devices and conductors. The memory transistors have thicker sidewall insulating layer to prevent the charge stored in the memory device from adversely influencing the operation of the memory transistor.
REFERENCES:
patent: 5190887 (1993-03-01), Tang et al.
patent: 5313419 (1994-05-01), Chang
patent: 5412238 (1995-05-01), Chang
patent: 5702988 (1997-12-01), Liang
patent: 5717634 (1998-02-01), Smayling et al.
patent: 6037222 (2000-03-01), Huang et al.
patent: 6043123 (2000-03-01), Wang et al.
patent: 6096597 (2000-08-01), Tsu et al.
patent: 6141242 (2000-10-01), Hsu et al.
patent: 6146970 (2000-11-01), Witek et al.
patent: 6174759 (2001-01-01), Verhaar et al.
patent: 6180456 (2001-01-01), Lam et al.
patent: 6207501 (2001-03-01), Hsieh et al.
patent: 6228712 (2001-05-01), Kawai et al.
patent: 6258667 (2001-07-01), Huang
patent: 6284602 (2001-09-01), He et al.
patent: 6368907 (2002-04-01), Doi et al.
patent: 6406960 (2002-06-01), Hopper et al.
patent: 2002/0025635 (2002-02-01), Kwon
patent: 2002/0041000 (2002-04-01), Watanabe
patent: 0 810 667 (1997-12-01), None
patent: 0 997 930 (2000-05-01), None
patent: 02-260564 (1990-10-01), None
Flynn Nathan J.
Infineon - Technologies AG
Slater & Matsil L.L.P.
Wilson Scott R.
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