Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-05
2004-03-09
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S311000, C438S591000
Reexamination Certificate
active
06703275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. More particularly, the invention relates to a flash memory cell having a silicon-oxide-nitride-oxide-silicon (SONOS) structure in which silicon, an oxide film, a nitride film, an oxide film and silicon are sequentially stacked, and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell.
2. Description of the Prior Art
A flash memory cell is a non-volatile memory device that is electrically programmed and erased. A basic structure and programming/erasing operation of the flash memory cell will be described below.
FIG. 1
is a cross-sectional view of a conventional flash memory cell for describing the structure and programming/erasing operation of the flash memory cell.
As shown in
FIG. 1
, the flash memory cell includes a tunnel oxide film
12
, a floating gate
13
consisting of a first polysilicon layer, an ONO dielectric film
14
, a control gate
15
consisting of a second polysilicon layer, and source and drain
16
a
,
16
b
that are formed at both edges of the tunnel oxide film
12
, all of which are sequentially stacked on a semiconductor substrate
11
.
In the flash memory cell constructed above, if the control gate
15
is applied with a high voltage of about 9V and the drain
16
b
is applied with a voltage of about 5V having about 5 &mgr;s pulse, channel hot electrons generated on the surface of the semiconductor substrate
11
below the gate oxide film
12
. The generated hot electrons are then stored at the floating gate
13
through the gate oxide film
12
, so that a programming operation is performed.
Further, if the control gate
15
in the flash memory cell is applied with a negative voltage of about −9V and the semiconductor substrate
11
is applied with a high voltage of about 9V, the electrons stored at the floating gate
13
are discharged from the floating gate
13
based on a FN (Fwoler Nerdheim) tunneling effect, so that an erasing operation is performed.
The flash memory cell constructed above is formed by exposure/etching process several times. Therefore, there are problems that the process steps are complicated and obtaining a process margin is difficult. In addition, the conventional flash memory cell requires a large area compared to peripheral devices and only data of one bit per cell can be stored. Due to this, there is a problem that the efficiency is degraded in view of the level of integration.
Meanwhile, an edge portion of the tunnel oxide film is damaged by various etching and/or ion implantation processes for forming the control gate and the floating gate after a tunnel oxide film is thinly formed. Thus, there is a problem that the charge storage capacity of the floating gate is degraded. In this case, as a defective cell may occur in a worse case, there is a problem that reliability of the device and the process is degraded.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell, by which damage of a tunnel oxide film due to an ion implantation process can be prevented by first forming a source region and a drain region and then forming a tunnel oxide film, data of two bits can be stored at a single cell by forming independent two channel regions below a floating gate, and an electrical characteristic and integration level of a device can be improved and the number of the process can be reduced by forming a tunnel oxide film, a floating gate and a dielectric film to be an ONO structure at a given region.
In order to accomplish the above object, a flash memory cell according to the present invention, is characterized in that it comprises a tunnel oxide film formed at a given region of a SOI substrate; a floating gate on the tunnel oxide film; a dielectric film on the floating gate; first and second channel regions at the SOI substrate below both ends of the floating gate; a source region formed between the first and second channel regions; first and second drain regions at the SOI substrate at both sides of the floating gate; and a word line formed on the dielectric film, wherein data of two bits or four bits are stored at a single cell by individually injecting electrons into the floating gate on the first and second channel regions or discharging the injected electrons, depending on voltages applied to the source region, the word line, and the first and second drain regions.
A method of manufacturing a flash memory cell according to a first embodiment of the present invention, is characterized in that it comprises the steps of forming a P type impurity region and a source region at a SOI substrate; forming a drain region consisting of a N type impurity region at the central region of the P type impurity region; forming a device isolation film on the drain region; forming a tunnel oxide film, a floating gate and a dielectric film having a stack structure on the source region and the P type impurity region, wherein the tunnel oxide film, the floating gate and the dielectric film being are separated by the device isolation film and both ends of the tunnel oxide film, the floating gate and the dielectric film are overlapped with a portion of the P type impurity region; and forming a conductive material layer and then forming a word line by means of an etching process using a word line mask.
A method of manufacturing a flash memory cell according to a second embodiment of the present invention, is characterized in that it comprises the steps of forming a P type impurity region and a source region at a SOI substrate; forming a drain region consisting of a N type impurity region at the central region of the P type impurity region; forming a device isolation film at the drain region, and a tunnel oxide film at the P type impurity region and the source region, by means of a thermal oxidization process; forming a floating gate and a dielectric film having a stack structure on the tunnel oxide film; and forming a conductive material layer and then forming a word line by means of an etching process using the word line as a mask.
In the above, the floating gate consists of a nitride film, and the tunnel oxide film, the floating gate and the dielectric film has an ONO structure.
After a flash memory cell is manufactured, an interlayer insulating film is formed on the entire structure and a contact plug is then formed to be connected with given regions of a source region and a drain region. At this time, the contact plug is formed one by one every 5 through 10 cells. The number of the contact plug is adjusted depending on a design rule or a voltage to be applied.
A method of programming a flash memory cell according to a first embodiment of the present invention, is characterized in that it, in a state that a word line is applied with a program voltage and a source region is connected to a ground terminal, a second drain region is connected to a ground terminal and a first drain region is applied with a voltage of about 5V, in case that electrons are injected into one end of a floating gate consist of a nitride film; and the first drain region is connected to the ground terminal and the second drain region is applied with a voltage of about 5V, in case that the electrons are injected into the other end of the floating gate, whereby electrons are independently injected into one end and the other end of the floating gate to store data of two bits at a single cell.
A method of programming a flash memory cell according to a second embodiment of the present invention, is characterized in that it, in a state that the word line is applied with a program voltage and the source region is applied with a voltage of about 5V, the first drain region is connected to the ground terminal and the second dr
Ahn Byung Jin
Chung Sung Jae
Park Byung Soo
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Lebentritt Michael S.
LandOfFree
Flash memory cell and method of manufacturing the same, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory cell and method of manufacturing the same, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory cell and method of manufacturing the same, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3236142