Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-09-19
2006-09-19
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S253000
Reexamination Certificate
active
07109082
ABSTRACT:
A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.
REFERENCES:
patent: 2002/0012745 (2002-01-01), Kanamori
patent: 2002/0167041 (2002-11-01), Tseng
patent: 2004/0048482 (2004-03-01), Tseng
patent: 2005/0173756 (2005-08-01), Kim et al.
Huang Cheng-Tung
Pittikoun Saysamone
Wang Leo
Jianq Chyun IP Office
Le Thao P.
Powerchip Semiconductor Corp.
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