Flash memory array structure and method of forming

Details Flash memory array structure and method of forming Flash memory array structure and method of forming

2002-06-20

2003-05-20

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S430000, C438S433000, C438S524000

Reexamination Certificate

active

06566200

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a flash memory array structure and method of forming.
BACKGROUND OF THE INVENTION
Many non-volatile memory devices are fabricated with semiconductor materials. One such non-volatile memory device is a flash memory array. Flash memory arrays are semiconductor devices that are formed from an array of memory cells with each cell having a floating gate transistor that includes a source, a drain, a floating gate, and a control gate. The sources of each floating gate in each cell are connected to form a source line.
The floating gate transistors of a flash memory array are electrically isolated from one another by isolation structures. One type of isolation structure used is a Shallow Trench Isolation (“STI”) structure. STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric material. STI structures used in flash memory arrays result in high resistance of the source line, which reduces the operational performance of the memory. In addition, in flash memory arrays there is only one source contact for each source line, which is coupled to the sources of each memory cell in a line of memory cells. Therefore, each memory cell has a different source resistance depending on the location of the memory cell with respect to the source contact. This results in a wide threshold voltage distribution for the entire flash memory array.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.
Embodiments of the invention provide a number of technical advantages. Embodiments of the invention may include all, some, or none of these advantages. Source line resistance in flash memory arrays may be substantially reduced or eliminated. In addition, a tight flash memory array threshold voltage (“Vt”) distribution may be obtained.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 5885896 (1999-03-01), Thakur et al.
patent: 6040231 (2000-03-01), Wu
patent: 6218265 (2001-04-01), Colpani
patent: 6303480 (2001-10-01), Desai et al.
patent: 6417555 (2002-07-01), Ueno et al.

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