Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-19
2001-07-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000
Reexamination Certificate
active
06255170
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a flash memory device and a method for fabricating the same that reduces source line resistivity and a device chip size.
2. Background of the Related Art
FIG. 1A
illustrates a plan view of a background art flash memory, and
FIG. 1B
illustrates a cross section along line I—I in the device of FIG.
1
A. Referring to
FIGS. 1A and 1B
, the background art flash memory is provided with a plurality of tunnel oxide films
2
and floating gates
3
stacked over a semiconductor substrate
1
. Gate oxide films
4
, control lines
5
and gate cap insulating films
6
are formed extending along one direction to cover the floating gates
3
. Source regions
7
a
are formed in the semiconductor substrate
1
along one side of the control gate lines
5
stacked over the floating gates
3
. The source regions
7
a
are connected outside the flash memory device through one self-aligned source contact region
7
.
Sidewall spacers
8
are formed on both sides of the tunnel oxide film
2
, the floating gate
3
, the gate oxide film
4
, the control gate line
5
and the gate cap insulating film
6
. However, the sidewall spacers
8
between the floating gates
3
above the source contact region
7
are further etched down to sides of the gate oxide films
4
. Drain regions
9
a
are formed in the semiconductor substrate
1
on the other side of the control gate lines
5
stacked over the floating gates
3
, and bit line contact regions
9
are formed to expose the drain regions
9
a
. Bit line wirings
10
in contact with the bit line contact regions
9
are disposed in a direction perpendicular to the control gate lines
5
.
As described above, the background art flash memory has various problems. The source resistance difference of flash memory cells coming from different positions in the array causes non-uniformity in programming and read. In the case of the background art flash memory cell having an SAS process applied thereto, the source resistance difference varies between 100 ohms to 2000 ohms depending on the cell position in an array, which causes non-uniformity of a programming voltage and cell current in programming and reading. The unequal programing voltages and cell currents within the cell array that reduce efficiency of the programming and reading operations. Further, the exposure of the gate oxide film, an inter poly dielectric, to an etching ambient when spacers are formed at sides of the source contact region by an anisotropic etching can damage the gate oxide film. In addition, as a cell size is reduced, it is difficult to secure spaces between adjacent bit lines formed in the bit line contact portions on the drain regions. That is, layout tolerances for active regions and bit lines are decreased because the bit line contacts are disposed on a straight line.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is directed to a semiconductor device and a method for fabricating the semiconductor device that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor device and a method for fabricating the same that reduces a source region resistance.
Another object of the present invention is to provide a flash memory and a method for fabricating the same that prevents a reduced bit line lay-out tolerance.
Another object of the present invention is to provide a flash memory and a method for fabricating a flash memory that dispenses with active lines and metal lines for source lines.
Another object of the present invention is to provide a flash memory and a method for fabricating a flash memory that reduces an effective cell size.
To achieve these and other objects and advantages in a whole or in parts and in accordance with the purpose of the present invention as embodied and broadly described, a semiconductor device includes a matrix of first gates on a semiconductor substrate, a plurality of second gates extending along a first direction to cover the first gates, source and drain regions formed adjacent the first gates on opposing sides of the second gates, a conductive layer contacting the source regions at source contact regions and second lines extending in a second direction substantially perpendicular to the first direction, wherein the second lines contact the drain regions at bit line contact regions, wherein the bit line contact regions in adjacent second lines are offset in the second direction.
To further achieve the above objects in a whole or in parts, there is provided a flash memory device according to the present invention that includes floating gates stacked on tunnel insulating films on a plurality of prescribed regions of a semiconductor substrate, a plurality of control gate lines extending in a first direction with a zigzag pattern to cover the floating gates, wherein a distance between adjacent control gate lines varies between first and second prescribed distances, source regions in the semiconductor substrate between adjacent floating gates that are separated by the second prescribed distance, drain regions in the semiconductor substrate between said adjacent floating gates that are separated by the first prescribed distance, source contact regions that expose the source regions, drain contact regions that expose the drain regions, a first line over the control gate lines and the semiconductor substrate excluding the drain regions, wherein the first line is coupled to the source regions through the source contact regions and a plurality of second lines extending in a second direction perpendicular to the first direction, wherein the second lines are coupled to the drain regions through the drain contact regions.
To further achieve the above objects in a whole or in parts, there is provided a method for fabricating a flash memory according to the present invention that includes forming floating gates stacked on tunnel insulating films on a plurality of prescribed regions of a semiconductor substrate, forming a plurality of control gate lines extending in a first direction to cover the floating gates, wherein a distance between adjacent control gate lines varies between first and second prescribed distances, forming sidewall spacers on both sides of the floating gates and the control gate line, respectively forming source regions and drain regions in the semiconductor substrate on opposite sides of the floating gates and the control gate lines between the sidewall spacers, depositing a first interlayer insulating film on the semiconductor substrate, forming source contact regions that expose the source regions through the first interlayer insulating film, depositing a conductive layer on the first interlayer insulating film coupled to the source contact regions, removing portions of the conductive layer on the drain regions to form a common source, depositing a second interlayer insulating film on the semiconductor substrate, forming drain contact regions that expose the drain regions through the second interlayer insulating film and forming bit lines extending in a direction perpendicular to the first direction coupled to the drain contact regions, wherein bit line contact regions in adjacent bit lines are offset in the second direction.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 3956865 (1976-05-01), Schmermund
patent: 4084393 (1978-04-01)
Booth Richard
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
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