Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-19
2002-07-30
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S261000, C438S263000, C438S267000
Reexamination Certificate
active
06426257
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flash memory, which is a non-volatile semiconductor memory device, and more specifically to a flash memory that has an erase gate for the purpose of extracting electrons from a floating gate during erasing, and to a manufacturing method therefor.
2. Related Art
In the past, a known flash memory has a control gate for the purpose of performing control during data reading and data writing operations with respect to a floating gate, and also an erase gate, independent from the control gate, for performing erasing of with respect to the floating gate.
The above-noted type of flash memory is shown in the plan view presented in
FIG. 3
, and the cross-sectional view along the line x—x of
FIG. 3
is shown in FIG.
4
. In this flash memory, an activated region that is separated by an element separation oxide film
2
is provided on the surface of a p-type substrate
1
, and a floating gate
12
is provided at the top of the channel region between a source region
14
a
and drain region
14
b
, via an intervening gate insulation film
3
. On top of the above-noted structure is provided a linear controls gate
11
, which is a word line, via an intervening insulating film
8
. An erase gate
13
is provided so as to overlap with the edge of the floating gate
12
.
In a flash memory such as noted above, the condition in which data has been written into the memory is a condition in which electrons are injected into the floating gate, and in which the threshold voltage of the memory transistor is high. The erase condition is the condition in which electrons are released from the floating gate, and the threshold voltage is low.
Erasing in this flash memory is performed by utilizing the Fowler-Nordheim (F-N) tunneling current, so as to extract electrons from the corner edge part of the floating gate by the erase gate. As shown in
FIG. 5
, if the potential of the erase gate
13
is made high, an electronic field that is shown by the electrical force lines
21
is generated in an insulation film
10
that is between the floating gate
12
and the erase gate
13
(this film hereinafter being referred to simply as the FG-EG insulation film).
Compared to a location at which the insulation film is parallel, at the corner edge
15
of the floating gate
12
there is a concentration of the electrical field as shown in
FIG. 5
, the result being that there is a reduction in the effective thickness of the insulation film, this enabling a tunneling phenomenon to occur through the edge
15
part, whereby electrons migrate from the floating gate
12
to the erase gate
13
.
When performing operations other than erasing, such as reading and writing, although the potential of the erase gate decreases, because at the curved part
16
of the opposing gate surface from the edge because the electrical field is in fact even weaker than at the parallel part
17
of the FG-EG insulation film, ideally there is no electron flow through the edge
15
, and there is also no flow of electrons through the parallel part
17
. That is, the erase gate functions as a gate for only erasing.
An FG-EG insulation film of the past was formed by thermal oxidation of the floating gate, which is formed from polysilicon. However, the silicon oxide film that is formed by this thermal oxidation, as shown in
FIG. 6
, usually has an edge at which the film thickness is small. When the edge part becomes thin, the floating gate potential is caused to rise by operations other than erasing, so that when, for example, performing readout, electrons are ejected through the thin edge part, this leading to the problem of changing to the data writing condition (which is known as the disturb effect).
If an attempt is made to form a thick thermally oxidized film, because of the resulting rounding of the edge at the corner of the floating gate, there is the problem of a lowering of the concentration of the electric field during erasing, so that erasing is insufficient.
Accordingly, it is an object of the present invention to provide, in consideration of the above-noted drawbacks in the prior art, a flash memory and a manufacturing method therefor which reduce the above-described disturb effect and provide a flash memory having long-term reliability.
SUMMARY OF THE INVENTION
The present invention is a flash memory which is provided with a floating gate, a control gate, and an erase gate, said gates being mutually insulated from one another, in which the erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said opposing erase gate, wherein said insulation film between said floating gate and said erase gate having a uniform thickness at a corner part of said floating gate.
It is desirable that the above-noted floating gate be made of polysilicon, and that the above-noted FG-EG insulation film be made of either a silicon oxide film or a silicon oxide nitride film.
Another aspect of the present invention is a method for manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, said gates being mutually insulated from one another, in which the erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said opposing erase gate, said method comprising the steps of: forming said floating gate which is made of polysilicon and exposing a corner surface of said floating gate; and forming a silicon oxide film on said floating gate that is processed to a prescribed shape, using a CVD process.
Another aspect of the present invention is a method for manufacturing a flash memory which is provided with a floating gate, a control gate, and an erase gate, said gates being mutually insulated from one another, in which the erasing of data is performed by extracting electrons from an edge of a corner of said floating gate via an insulation film, into said opposing erase gate, said method comprising the steps of: forming said control gate which is made of polysilicon and forming a side wall of said control gate; forming a floating gate which is made of polysilicon by using said side wall as a mask; exposing a corner edge of said floating gate; forming a silicon oxide film having a uniform thickness at a corner part of said floating gate; and forming said erase gate.
Another aspect of the present invention is a method for manufacturing a flash memory including a step of annealing after said step of forming a silicon oxide film on the floating gate, using a CVD process.
Another aspect of the present invention is a method for manufacturing a flash memory including a step of forming a silicon thermal oxide film, after said step of forming a silicon oxide film on the floating gate, using a CVD process.
Another aspect of the present invention is a method for manufacturing a flash memory including a step of performing thermal oxidation in an oxidizing atmosphere that includes a nitrogen compound, after said step of forming a silicon oxide film on the floating gate, using a CVD process.
In a flash memory according to the present invention, because the FG-EG insulation film is formed so as to have a uniform thickness at the corner part thereof, the disturb effect does not occur, and long-term stability is achieved.
FIG. 3
shows a plan view of an example of a flash memory according to the present invention, and
FIG. 4
shows a cross-sectional view thereof, along the direction indicated by the x—x line in FIG.
3
. In this flash memory, activated region that is separated by an element separation film
2
is provided on the surface of a p-type substrate
1
, and a floating gate
12
is provided at the top of the channel region between a source region
14
a
and drain region
14
b
, via an intervening gate insulation film
3
. On top of the above-noted structure is provided a linear control gate
11
, which is a word line, via an intervening insulating film
8
. An erase gate
13
is provided so as to overla
Chen Jack
Hutchins, Wheeler & Dittmar
Nguyen Tuan H.
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