Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2003-03-19
2011-10-18
Chery, Mardochee (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S206000, C711SE12008, C711SE12014, C711SE12019
Reexamination Certificate
active
08041878
ABSTRACT:
The flash file system includes a flash memory and a subsystem interfacing between the flash memory and a host system. The subsystem includes a hierarchical structure of a host system interface, cache memory system, flash translation layer unit and a flash memory interface. The host system interface interfaces with the host system. The cache memory system has a storage capacity of a predetermined number of data units and stores data for transfer to and from the host system via the host system interface. The flash translation layer unit maps a logical address received from the host system via the host system interface and the cache memory into a physical address of the flash memory. The flash memory interface interfaces with the flash memory to transfer data to the flash memory from the cache memory system based on the physical address received from the flash translation layer unit and to transfer data from the flash memory to the cache memory system based on the physical address received from the flash translation layer unit.
REFERENCES:
patent: 5602987 (1997-02-01), Harari et al.
patent: 6016530 (2000-01-01), Auclair et al.
patent: 6145051 (2000-11-01), Estakhri et al.
patent: 6275436 (2001-08-01), Tobita et al.
patent: 2003/0033573 (2003-02-01), Tamura et al.
Chery Mardochee
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
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