Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-12-29
2008-08-26
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S262000, C257S317000, C257S318000, C257SE21682
Reexamination Certificate
active
07416944
ABSTRACT:
In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed in the word line direction, an interlayer polysilicon oxide film formed on a floating gate, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N+region formed in the semiconductor substrate under the source and drain electrodes, and a metal silicide film formed on an upper surface of the control gate.
REFERENCES:
patent: 5635415 (1997-06-01), Hong
patent: 6221718 (2001-04-01), Hong
patent: 6599680 (2003-07-01), Lin
patent: 2002/0142546 (2002-10-01), Kouznetsov et al.
Coleman W. David
Dongbu Electronics Co. Ltd.
Kim Su C
McKenna Long & Aldridge LLP
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