Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-21
1999-09-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438265, 257321, H01L 21336
Patent
active
059602856
ABSTRACT:
A floating gate transistor is formed on an active device region defined between field isolation structures. A first polysilicon layer, or a layer of another conductor which can be used in diffusing impurities into the underlying silicon substrate, is provided on the active device region of the substrate and is covered by a layer of insulating material such as silicon oxide. The first polysilicon layer is doped by implantation of impurities, but no annealing step is performed at this time. An opening is formed through the polysilicon layer to expose the surface of the active device region. Oxide spacers and then nitride spacers are formed on the sidewalls of the opening in the first polysilicon layer to define a narrower opening. A gate oxide layer is grown on the active device region between the nitride spacers in a thermal oxidation process which preferably causes impurities to diffuse from the first polysilicon layer into the active device region on either side of the gate electrode, forming source/drain regions for the floating gate transistor. The nitride spacers are then removed in a wet etching process and then tunnel oxide layers are grown on the portions of the active device region exposed when the nitride spacers are removed. A second layer of polysilicon is deposited, followed by an interlayer dielectric and then a third layer of polysilicon. Patterning defines a control gate and a floating gate from the third and second layers of polysilicon, respectively, for the floating gate transistor.
REFERENCES:
patent: 5273923 (1993-12-01), Chang et al.
patent: 5516713 (1996-05-01), Hsue et al.
patent: 5686332 (1997-11-01), Hong
patent: 5756385 (1998-05-01), Yuan et al.
Wolf, S.; Silicon Processing for the VLSI Era, vol. 2; Lattice Press, Sunset Beach, Ca.; pp. 153-160, 332-334, 1990.
Berezny Neal
Niebling John F.
United Semiconductor Corp.
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