Flash/dynamic random access memory field programmable gate...

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S063000, C365S189110

Reexamination Certificate

active

11484244

ABSTRACT:
A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.

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patent: 2005010889 (2005-02-01), None
Supplementary European search report in corresponding EP Application No. 04778193.5 (PCT/US2004/02256), Sep. 9, 2006, pp. 1-3.

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