Flash/dynamic random access memory field programmable gate...

Details Flash/dynamic random access memory field programmable gate... Flash/dynamic random access memory field programmable gate...

2006-10-10

2006-10-10

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S063000, C365S189110

Reexamination Certificate

active

07120079

ABSTRACT:
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

REFERENCES:
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European Patent Application No.: 04 778 193.5, European Patent Office supplementary search report under Article 157(2)(a) EPC, pp. 1-3, Jun. 6, 2006, and cover letter from foreign asociate received by Sierra Patent Group, Ltd. on Jun. 27, 2006.

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