Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-12-05
2006-12-05
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07146548
ABSTRACT:
An arrangement that includes a core with a flaw is effectively made error free with an auxiliary circuit that interacts with input and output leads of the core, which detected occurrence of an input that causes an erroneous output at the core, and modified that output either essentially directly, or through changes in accessible core inputs.
REFERENCES:
patent: 5644578 (1997-07-01), Ohsawa
patent: 6877122 (2005-04-01), Whetsel
Brendzel Henry T.
DAFCA, Inc.
Kerveros James C
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