Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-10-30
2007-10-30
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000
Reexamination Certificate
active
10853423
ABSTRACT:
A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2relative to osc1in a configurable way to provide a constant, minimal Tptccover a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2is a delayed, synchronous clock.
REFERENCES:
patent: 5923193 (1999-07-01), Bloch et al.
patent: 6516420 (2003-02-01), Audityan et al.
patent: 6738917 (2004-05-01), Hummel et al.
patent: 7110423 (2006-09-01), Sethuram et al.
patent: 7111184 (2006-09-01), Thomas et al.
patent: 2002/0087909 (2002-07-01), Hummel et al.
Gower Kevin C.
Griffin Thomas J.
Hnatko Steven J.
Lamb Kirk D.
VanStee Dustin J.
Augspurger Lynn L.
Brown Michael J.
Perveen Rehana
LandOfFree
Fixed latency data computation and chip crossing circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fixed latency data computation and chip crossing circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fixed latency data computation and chip crossing circuits... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3901235