First-in first-out memory device and method of generating...

Details First-in first-out memory device and method of generating... First-in first-out memory device and method of generating...

2001-09-10

2002-10-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S230050, C365S189120, C365S240000, C365S189070

Reexamination Certificate

active

06463000

ABSTRACT:

CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 2000-82094, filed on Dec. 26, 2000, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a first-in first-out (FIFO) memory device and a method of generating a flag signal in the same.
2. Description of Related Art
In communication between different processors (or systems) having different data rates, there generally exists a difference between the speed at which one processor (or system) writes data and the speed at which the other processor (or system) reads data. The first-in first-out (FIFO) memory device is used to control data transmission between different processors having different data rate.
FIG. 1
is a block diagram illustrating data transmission between processors according to conventional art. Processors
10
and
12
and a FIFO memory device
14
are shown. As shown in
FIG. 1
, the processor
10
transfers input data IN to the FIFO memory device
14
, and the processor
12
receives data from the FIFO memory device
14
to output data OUT. The processor
10
is faster in data rate than the processor
12
.
The FIFO memory device
14
is reset in response to a reset signal output from the processor
10
and is enabled in response to a write enable signal WEB transferred from the processor
10
and stores write data WD in response to a write clock signal WCK. If the FIFO memory device
14
becomes full, the FIFO memory device
14
transfers a full flag signal Full to the processor
10
so that the processor
10
cannot write data. Also, the FIFO memory device
14
is enabled in response to a read enable signal REB transferred from the processor
12
and transfers read data RD to the processor
12
in response to a read clock signal RCK. If the FIFO memory device
14
becomes empty, the FIFO memory device
14
transfers an empty flag signal Empty to the processor
12
so that the processor
12
cannot read data.
The FIFO memory device
14
of
FIG. 1
is configured to be reset in response to the reset signal output from the processor
10
but may be configured to be reset in response to a reset signal applied from another controller (not shown) other than the processors
10
and
12
.
As described above, the FIFO memory device
14
is arranged between the two processors
10
and
12
to facilitate data transfer between the different processors having different data rates.
FIG. 2
is a block diagram illustrating a configuration of the FIFO memory device of FIG.
1
. As shown in
FIG. 2
, the FIFO memory device includes a dual port memory cell array
20
, a write pulse generating circuit
22
, a write address generating circuit
24
, a write data register
26
, a read pulse generating circuit
28
, a read address generating circuit
30
, a read data register
32
, and a flag generating circuit
34
.
The dual port memory cell array
20
writes data in response to a write address WA and reads data in response to a read address RA. The write pulse generating circuit
22
generates an internal write clock signal iWCK in response to an inverted write enable signal WEB and a write clock signal WCK when the full flag signal Full is not active. The write address generating circuit
24
is reset in response to the reset signal and generates a write address WA in response to the internal write clock signal iWCK. The write data register
26
stores write data WD in response to the internal write clock signal iWCK to output it to the dual port memory cell array
20
. The read pulse generating circuit
28
generates an internal read clock signal iRCK in response to an inverted read enable signal REB and a read clock signal RCK when the empty flag signal Empty is not active. The read address generating circuit
30
is reset in response to the reset signal and generates a read address RA in response to an internal read clock signal iRCK. The read data register
32
outputs read data RD output from the dual port memory cell array
20
in response to the internal read clock signal iRCK. The flag generating circuit
34
compares a write address WA with a read address RA in response to the reset signal, and generates a full flag signal Full in response to an internal write clock signal iWCK and generates an empty flag signal Empty in response to an internal read clock signal iRCK when a write address WA and a read address RA are equal.
FIG. 3
is a circuit diagram illustrating a configuration of the dual port memory cell array of FIG.
2
. The dual port memory cell array includes an m_n-number of memory cells MC connected, respectively, between an n-number of write word lines wwl
1
to wwln and an m-number of write bit line pairs wbl
1
and wbl
1
b to wblm and wblmb, and between an n-number of read word lines rwl
1
to rwln and an m-number of read bit line pairs rbl
1
and rbl
1
b to rblm and rblmb.
As shown in
FIG. 3
, each of the memory cells MC includes NMOS transistors N
1
and N
2
for a write data transmission, NMOS transistors N
3
and N
4
for a read data transmission and a latch LA
1
having inverters I
1
and I
2
for a data latch.
The NMOS transistors N
1
and N
2
transfer data of the write bit line pairs wbl
1
and wbl
1
b to wblm and wblmb to nodes n
1
and n
2
in response to a signal transferred to the write word lines wwl
1
to wwln, respectively. The NMOS transistors N
3
and N
4
transfer data of the nodes n
1
and n
2
to the read bit line pairs rbl
1
and rbl
1
b to rblm and rblmb in response to a signal transferred to the read word lines rwl
1
to rwln, respectively. The latch LA
1
latches data of the nodes n
1
and n
2
.
FIG. 4
is a circuit diagram illustrating a configuration of the write address generating circuit of FIG.
2
. The write address generating circuit includes a column address generating circuit
40
and a row address generating circuit
42
. The column address generating circuit
40
includes n-bit serial sequential shift registers WCA
0
to WCA(n−1), and the row address generating circuit
42
includes m-bit serial sequential shift registers WRA
0
to WRA(m−1).
The n-bit serial sequential shift registers WCA
0
to WCA(n−1) include a register WCA
0
and registers WCA
1
to WCA(n−1). The register WCA
0
includes a master portion having a CMOS transmission gate C
1
, an NMOS transistor NM
1
and a latch LA
2
having inverters I
3
and I
4
, and a slave portion having a CMOS transmission gate C
2
and a latch LA
3
having inverters I
5
and I
6
. Each of the registers WCA
1
to WCA(n−1) includes a master portion having a CMOS transmission gate C
3
, a PMOS transistor PM
1
and a latch LA
4
having inverters I
7
and I
8
and a slave portion having a CMOS transmission gate C
4
and a latch LA
5
having inverters I
9
and I
10
.
The m-bit serial sequential shift registers WRA
0
to WRA(m−1) include a register WRA
0
having the same configuration as the register WCA
0
, and registers WRA
1
to WRA(m−1) having the same configuration as the registers WCA
1
to WCA(n−1).
The write address generating circuit further includes inverters I
11
and I
12
, and a control circuit
44
. The inverter I
11
inverts an internal write clock signal iWCK to control the CMOS transmission gates C
1
to C
4
of the n-bit serial sequential shift registers WCA
0
to WCA(n−1). The inverter I
12
inverts a reset signal to control the NMOS transistor NM
1
and the PMOS transistor PM
1
of the shift registers WCA
0
to WCA(n−1) and WRA
0
to WRA(m−1). The control circuit
44
generates a control signal to control the CMOS transmission gates C
1
to C
4
of the m-bit serial sequential shift registers WRA
0
to WRA(m−1).
Operation of the write address generating circuit of
FIG. 4
is described in accordance with the following. The PMOS transistor PM
1
and the NMOS transistor NM
1
of the n-bit serial sequential shift registers WCA
0
to WCA(n−1) and the m-bit serial sequential shift registers WRA
0
to

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