First-in first-out memory

Details First-in first-out memory First-in first-out memory

1990-12-13

1993-12-28

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518901, 36518904, G11C 1300, G11C 1140

Patent

active

052746003

ABSTRACT:
A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.

REFERENCES:
patent: 5025422 (1991-06-01), Moriwaki et al.
patent: 5031149 (1991-07-01), Matusumoto et al.
"CMOS Parallel Synchronous FIFO 512.times.18-Bit & 1024.times.18-Bit," by Integrated Device Technology, Incorporated, Jul. 1990, pp. 1-15.
"CMOS Parallel Sync FIFO (Clocked FIFO) 512.times.18-Bit and 1024.times.18-Bit," Paper 6.13, Integrated Device Technology, Inc., Aug. 1990, pp. 1-22.

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