Static information storage and retrieval – Read/write circuit – Serial read/write
Patent
1989-12-01
1991-05-14
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Serial read/write
36518907, G11C 700
Patent
active
050162217
ABSTRACT:
A first-in, first-out (FIFO) memory configuration comprising a fully addressable memory (e.g. random access memory), a write pointer, a read pointer, and a third, "commit" pointer serving as a boundary between first and second subsets of data stored within the FIFO. During data reception, a comparator circuit compares a predetermined subset of imcoming data with a predefined reference data set for determining whether the incoming data should be stored or aborted. This determination establishes the appropriate memory address value for positioning the commit pointer. The first subset of data behind the commit pointer may selectively be stored, while the second subset of data ahead of the commit pointer may selectively be aborted. During data transmission, a status register monitors the readiness of the data medium onto which the data is to be transmitted. If and/or when the data medium is ready to accept data, the commit pointer may be selectively positioned to demarcate data committed for transmission.
REFERENCES:
patent: 3979733 (1976-09-01), Fraser
patent: 4095283 (1978-06-01), Campbell et al.
patent: 4419746 (1983-12-01), Hunter et al.
patent: 4433394 (1984-02-01), Torii et al.
patent: 4507760 (1985-03-01), Fraser
National Semiconductor Corporation
Popek Joseph A.
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