First-in, first-out (FIFO) buffer

Details First-in, first-out (FIFO) buffer First-in, first-out (FIFO) buffer

1997-02-13

1998-11-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518905, G11C 700

Patent

active

058417222

ABSTRACT:
A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided.
One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.

REFERENCES:
patent: 4833655 (1989-05-01), Wolf et al.
patent: 5331598 (1994-07-01), Matsushita et al.
patent: 5513145 (1996-04-01), Hattori et al.

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