FinFET memory cell having a floating gate and method therefor

Details FinFET memory cell having a floating gate and method therefor FinFET memory cell having a floating gate and method therefor

2007-08-08

2010-10-12

Ha, Nathan W (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21219

Reexamination Certificate

active

07811889

ABSTRACT:
A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.

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patent: 7091551 (2006-08-01), Anderson et al.
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patent: 2006/0278915 (2006-12-01), Lee et al.
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patent: 2008/0080248 (2008-04-01), Lue et al.
patent: 2009/0032859 (2009-02-01), Zhu

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