FinFET device incorporating strained silicon in the channel...

Details FinFET device incorporating strained silicon in the channel... FinFET device incorporating strained silicon in the channel...

2002-12-31

2004-10-05

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S411000, C257S412000, C257S413000, C257S347000

Reexamination Certificate

active

06800910

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to semiconductor devices, and more particularly to vertical double gate MOSFETs, also known as FinFETs.
2. Related Technology
Metal oxide semiconductor field effect transistors (MOSFETs) are the primary component of most semiconductor devices. The conventional MOSFET is constructed from a semiconductor substrate in which dopant-implanted active regions are formed. As a result, the active components of the MOSFET are surrounded by semiconductor material. However, as channel lengths are reduced to less than 100 nm, the use of semiconductor substrate construction in MOSFETs creates performance degrading phenomena such as short channel effect. The short channel effect degrades the ability of the MOSFET gate to control conductivity in the MOSFET channel region due to interactions of the source and drain regions that occur as a result of the semiconductor materials of the semiconductor substrate that surround the active regions.
An alternative to the conventional semiconductor substrate construction is silicon on insulator (SOI) construction. In SOI construction, devices such as MOSFETS are formed as monolithic semiconductor structures supported on a dielectric substrate, rather than as regions formed within a semiconductor substrate. SOI devices have been found to have a number of advantages over devices formed using semiconductor substrate construction, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions.
One type of MOSFET structure that is formed using SOI construction is conventionally known as a vertical double-gate MOSFET, or a FinFET. As shown in
FIG. 1
a
, the FinFET is constructed from a silicon body that includes a source region
12
, a drain region
14
and a fin-shaped channel region
16
. The source
12
, drain
14
and channel
16
regions are formed of a monolithic silicon body that is patterned from a silicon layer provided on a dielectric substrate
18
. After patterning the silicon body, a gate oxide is grown or deposited over the silicon body, and then a conductive gate
20
as shown in
FIG. 1
b
is patterned so as to surround the channel region
16
. The gate
20
is patterned from a conductive material such as polysilicon.
FIG. 2
shows a view of a cross-section of the gate and channel region of the FinFET of
FIG. 1
b
taken at line A-A′. As seen in
FIG. 2
, the gate
20
and channel region
16
are separated by the gate oxide
22
, and the gate
20
surrounds the channel region
16
on both of its sidewalls, thus serving as a double gate that imparts gate voltage to both sides of the channel region
16
. The channel width of a FinFET is therefore approximately double the height of the channel region fin, enabling a high driving current compared to semiconductor substrate MOSFETs of comparable size.
While the conventional FinFET provides the aforementioned advantages over MOSFETs formed on semiconductor substrates due to its SOI construction, some fundamental characteristics of the FinFET such as carrier mobility are the same as those of other MOSFETs because the FinFET source, drain and channel regions are typically made from conventional MOSFET semiconductor materials such as silicon.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a FinFET device that improves over conventional FinFETs by enhancing characteristics of the device such as carrier mobility.
In accordance with embodiments of the invention, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of strained silicon is then formed on the Silicon germanium FinFET body. A tensile strain is imparted to the epitaxial silicon as a result of differences in the dimensionalities of a relaxed intrinsic silicon lattice and the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET body. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.
In accordance with one embodiment of the invention, a silicon on insulator MOSFET device comprises a substrate comprising a dielectric layer. A FinFET body is formed on the dielectric layer. The FinFET body is typically silicon germanium. The FinFET body includes source and drain regions that have a channel region extending therebetween. A layer of strained silicon is formed on the surfaces of at least the channel region. A gate insulating layer is formed over at least the channel region to cover the strained silicon formed on surfaces of the channel region. A conductive gate surrounds the sidewalls and the top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon.
In accordance with another embodiment of the invention, a silicon on insulator MOSFET device is formed by initially providing a SOI substrate that includes a semiconductor layer overlying a dielectric layer. The semiconductor layer is typically silicon germanium. The semiconductor layer is patterned to form a FinFET body that includes source and drain regions and a channel region extending therebetween. A layer of strained silicon is then formed on the surfaces of at least the channel region. A gate insulating layer is formed over at least the strained silicon grown on the channel region to cover the strained silicon grown on the channel region. A conductive gate is then formed. The conductive gate surrounds sidewalls and a top portion of the channel region and is separated from the channel region by the gate insulating layer and the strained silicon.
In accordance with further alternatives, multiple FinFETs as described above may be combined to form CMOS devices, and FinFET bodies may be formed to have multiple channel-regions to thereby provide greater channel width.


REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6562665 (2003-05-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.

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