Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-11
2006-07-11
Luu, Chuong A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S199000, C438S258000
Reexamination Certificate
active
07074660
ABSTRACT:
A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is caused to recede by means of a nonlithographic process from contact trenches, which define the contact structures, before the formation of the contact structures. A distance a between the gate electrode and the contact structures is not subject to any tolerances due to the overlay of two independent lithographic masks. For a given extent of the gate electrode along the transistor fin, it is possible to minimize a distance A between the contact structures and thereby significantly increase the packing density of a plurality of fin field-effect transistors on a substrate compared with conventional devices.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 6583469 (2003-06-01), Fried et al.
patent: 6610576 (2003-08-01), Nowak
Yu, B., et al., “FinFET Scaling to 10nm Gate Length,” IEDM, 2002, pp. 251-254.
Infineon - Technologies AG
Luu Chuong A.
Slater & Matsil L.L.P.
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