Final stage clock buffer in a clock distribution network

Details Final stage clock buffer in a clock distribution network Final stage clock buffer in a clock distribution network

1996-05-01

1998-12-15

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

326 93, 327297, H03K 19096

Patent

active

058501509

ABSTRACT:
A final stage clock buffer for use in a clock distribution network in a circuit with scan design includes a demultiplexer circuit and a control circuit. The buffer receives an input clock signal and outputs a clock signal and a scan clock signal. The buffer can operate in a functional mode, a scan mode and a hold mode. The demultiplexer circuit receives the input clock signal and a scan enable signal. The scan enable signal, when asserted, causes the buffer to enter the scan mode. In the scan mode, the demultiplexer circuit propagates the input clock signal to a scan clock terminal and a constant logic level to a clock terminal. When the scan enable signal is deasserted, the demultiplexer circuit propagates the input clock signal to the clock terminal and a constant logic level to the scan clock terminal. The control circuit receives a chip-enable signal. When the chip-enable signal is asserted while the scan signal is deasserted, the buffer enters the functional mode. The asserted chip-enable signal causes the control circuit to allow the input clock signal to continue to propagate to the clock terminal. When both the chip-enable signal and the scan signal are deasserted, the buffer enters the hold mode. The deasserted chip-enable signal causes the control circuit to stop the propagation of the input clock signal to the clock output terminal and, instead, causes the clock signal to remain in a constant logic state.

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Wakerly, John F.; "Digital Design: Principles and Practices",copyright Sep. 1989 by John F. Wakerly;pp. 274-275.

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