Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-08
2001-10-23
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S022000
Reexamination Certificate
active
06308292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to error detection of a semiconductor device, and more particularly to generating a test pattern for testing systems.
2. Description of Related Art
Microelectronic integrated circuits (ICs), such as computer chips, are used in a variety of products including personal computers, automobiles, communication systems, and consumer electronics products. Typically, an IC contains millions of microscopic electrical components and is fabricated on wafers of silicon. As the popularity of ICs has increased, techniques for designing ICs, such as Computer Aided Design (CAD), have become simpler and more economical.
The lowered cost of designing ICs allows smaller high-tech companies to create their own custom made, or Application Specific ICs (ASICs), instead of using “off-the-shelf” generic IC packages. While many large scale businesses can afford the necessary equipment to manufacture their ICs, a small company often does not have such equipment. These businesses often create IC designs in-house and send their designs to an IC manufacturer who then fabricates, packages, and tests the IC. The process of creating ICs can therefore be divided into two separate tasks, design and manufacturing.
FIG. 1
illustrates a division between designing steps
101
and manufacturing steps
103
of IC production. The designer first abstracts the design using circuit design tools
105
. Circuit design tools typically allow the user to design a circuit using a top-down approach. The user starts the design with a high level functional description of the circuit and gradually works down to a lower register and gate level design representation. A top-down approach greatly simplifies the design process, enabling the engineer to concentrate on functional aspects of the design without having to worry about low-level circuit theory and device physics details.
The circuit design tools
105
typically generate circuit design files
107
and simulation files
109
. The design files
107
contain detailed information about analog and digital component interconnections, and are used in preparation of IC fabrication by the manufacturer. The simulation files
109
include a circuit description and simulation data used by a fault simulator and verification tools
111
, for example.
The design files
107
are received by the manufacturer's process tools
117
to define the physical layout and testing of the IC. The process tools
117
then generate process programs used by IC manufacturer's equipment. Fabrication
119
involves multiple stages of chemical and physical processing to create the actual IC having, for example, solid state transistors, solid state resistors, input/output pads, metal interconnections and so on. The fabricated IC
121
is encapsulated in plastic, ceramic, or other material according the designer's specifications.
The simulation files
109
include time sets used to create strobe signals. Strobes determine the time within each test cycle the manufacturer's test equipment
115
, such as an automatic test equipment (ATE) system, collects data from the IC's output signals. The simulation files
109
also include a circuit description, such as a circuit netlist or a Register Transfer Level (RTL) description, which is input into the simulator
111
. A netlist is typically a list of electronic logic cells with a description of the connections between the inputs and the outputs of the various logic cells. An RTL description describes the functionality of the circuit, much like programming source code is a description of the functionality of a software program.
Simulation permits the designer to test whether a particular design works before it is built. By using mathematical models for physical devices, a simulator can provide simulated best and worst case output results for a given input stimulus. Input stimulus represents a set of input signals required to drive specific functional aspects of the circuit during simulation. Generally, the input stimulus used in circuit simulation is created by the designer to simulate operation of the circuit design embodied in the design representation. The input stimulus is primarily based on anticipated real world conditions (e.g., the conditions of an IC found in a cellular phone) and on requirements for properly exercising particular functional blocks within the circuit. By comparing simulation results with expected simulation output, the designer can make sure his or her design works in anticipated real world conditions before actually building the IC.
A verification step further analyzes the simulation results and generates test files
113
. The test files
113
generally include test patterns and margin analysis data. Test patterns contain both IC input patterns and IC output patterns used by the manufacturer's test equipment
115
, such as an automatic test equipment (ATE) system. An IC input pattern is similar to simulation input stimulus and is used by the ATE system to drive input signals of the IC under test. An IC output pattern is similar to expected simulation output and is used to check the results from output signals of the IC under test.
An ATE system checks an IC by strobing the IC's output signals. The strobe signal allows the ATE system to collect IC output data from the output signal strobed. Data from the output signal is then compared with the output pattern in the test pattern to determine if the IC's output is correct. Crucial to this procedure is the output signal's “margin time.”
Margin time is the time between an output signal's expected, or simulated, data change and the output signal's associated strobe signal. Generally, a left margin time is calculated for an output transition occurring before the strobe, and a right margin time is calculated for an output transition occurring after the strobe. A positive left or right margin time indicates the simulated output signal's best and worst case data transitions occur on the same side of a strobe signal's outer edge. In other words, a positive margin time indicates the output signal's best and worst case data edges occur on only one side of the strobe signal. Negative margin times indicate an output signal's best and worst case data transitions occur on different sides of a strobe signal edge, or within the strobe signal.
Negative margin times are undesirable because the output signal's state is unknown during strobe. For negative margin times, the IC's best and worst case simulation indicate a data transition can occur at a time either before, during, or after a strobe edge. A test pattern cannot be generated to check the IC's output state during strobe if negative margin times exist. Thus, a negative margin time will cause a signal to fail the verification step. Small positive margin times close to zero may also be undesirable even though they will not cause a verification failure. The closer an IC output signal's margin time is to zero, the closer the manufactured IC must behave to the ideal IC. Thus, if an actual IC having only a two nanosecond left margin time outputs data three nanoseconds past the expected output time, it will fail the associated test cycle.
Various design, manufacturing, and operational conditions can cause a manufactured IC's performance to deviate from its ideal performance. For example, an IC manufacturing process may require baking IC silicon wafers in a furnace for a length of time. The wafers at the ends of the furnace may be heated to a lower temperature than the wafers in the middle of the furnace, causing small process changes that can result in device operating characteristic differences, including timing variations. Thus, the time an IC takes to output valid data may vary by a few nanoseconds within a given lot. The smaller the margin time becomes for a given test pattern, the higher the failure rate will be due to inevitable IC timing variations.
Typically, an IC manufacturer tests
LSI Logic Corporation
Tu Christine T.
LandOfFree
File driven mask insertion for automatic test equipment test... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with File driven mask insertion for automatic test equipment test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and File driven mask insertion for automatic test equipment test... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2616036