FIFO memory including dynamic memory elements

Details FIFO memory including dynamic memory elements FIFO memory including dynamic memory elements

1987-09-09

1989-11-21

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365219, 365221, 365222, 340799, G11C 700, G09G 102

Patent

active

048827100

ABSTRACT:
A FIFO memory is provided with individual arrays of dynamic memory cells and includes a dedicated write line buffer memory and a dedicated read line buffer memory operably connected thereto. First and second line buffer memories are also provided in conjunction with the write line buffer memory and the read line buffer memory so as to permit a faster response to the input and output of data with respect to the FIFO memory. Data may be alternately written into either one of the line buffer memories as a lead-in to the subsequent writing of data in the dynamic memory arrays via the write line buffer memory. Data read out from the other line buffer memory may occur simultaneously. The FIFO memory may serve as a video data frame memory for storing a frame of a video screen image. Where video data is continuously written into the FIFO memory, either the preceding video data frame or the current video data frame that is being written is subject to read out depending on the timing of a read reset signal relative to the last write reset signal. The write line buffer memory and the read line buffer memory are operable independently of each other, and may have simultaneous cycle times without any synchronization therebetween. The first and second line buffer memories preferably comprise static type memory elements to facilitate rapid data read out therefrom in response to a read reset signal.

REFERENCES:
patent: 4535427 (1985-08-01), Jiang
patent: 4547867 (1985-10-01), Reese et al.
patent: 4646270 (1987-02-01), Voss
patent: 4648032 (1987-03-01), Romero, Jr. et al.
Pai, "FIFO RAM Controller Tackles Deep Data Buffering", Computer Design, Aug. 1, 1986, pp. 109-112.
Tunick, "Rich with Logic, Memory ICs Hone Their Specialties", Electronic Design, Jun. 11, 1987, pp. 77-86.
"A 1 Mb DRAM with 33 MHz Serial I/O Ports"--Ohta et al., IEEE International Solid-State Circuits Conference, pp. 274-275, (Feb. 21, 1986), with Related Product Description, 1 MBit Image Memory MN4700 Product Description.
"1985 Memory Products Databook"--NEC Electronics Inc., .mu.PD41221 224,000-Bit Serial-Access NMOS RAM, pp. 3-21 through 3-25, (Jan. 1985).
"1986 Memory Databook"--NEC Electronics Inc., .mu.PD41221 224,000-Bit Serial-Access NMOS RAM, pp. 3-25 through 3-31, (Apr. 1986).

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