FIFO memory architecture

Details FIFO memory architecture FIFO memory architecture

2002-12-31

2004-08-17

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S039000

Reexamination Certificate

active

06777979

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to FIFO (first-in-first-out) memories, and more particularly to a FIFO memory architecture for use in programmable semiconductor devices such as programmable interconnect devices and programmable logic devices.
BACKGROUND
Programmable interconnect devices permit a user to programmably route signals between pins of the device. For example, Lattice Semiconductor Corp. currently offers a family of programmable interconnect devices having a non-volatile in-system-programmable crossbar switch matrix for programmable switching, interconnect, and jumper functions. In a programmable interconnect device or circuit, each pin is associated with an input/output (I/O) circuit that programmably couples other I/O circuits through a routing structure denoted as a global routing pool (GRP). Another programmable interconnect device is described in “Block Oriented Architecture for a Programmable Interconnect Circuit,” U.S. Ser. No. 10/022,464, filed Dec. 14, 2001, the contents of which are incorporated by reference in their entirety. In this programmable interconnect device, the I/O circuits are grouped together in a “block-oriented” architecture that contrasts with a “pin-oriented” architecture for a programmable interconnect device. In a pin-oriented architecture, the routing structure addresses each I/O circuit independently, whereas in a block-oriented architecture, the I/O circuits in a block are not addressed independently by the routing structure. By organizing the I/O circuits into blocks, the routing structure may be arranged in a two-level organization as described in “Multi-Level Routing Structure for a Programmable Interconnect Circuit,” U.S. Ser. No. 10/023,053, filed Dec. 14th, 2001, the contents of which are hereby incorporated by reference in their entirety. In addition, the routing structure may be subdivided into a data-path routing structure and a control-path routing structure as described therein.
A programmable interconnect device having a block-oriented architecture and a two-level routing structure as just described may be advantageously used in bus-switching applications. However, because of problems such as skew associated with high-speed parallel data transmission, parallel data is often serialized before transmission and then deserialized on reception using serial transmission protocols such as a low voltage differential signaling protocol (LVDS). To permit the transition between parallel and serial data transmission, serializer/deserializer (SERDES) units are conventionally incorporated at both the transmitting and receiving ends of the serial data stream. Encoded into the serial data stream is a clock signal independent of the device's internal (i.e., system) clock. To accommodate the two asynchronous reading and writing clocks, a first-in-first-out (FIFO) buffer memory (often referred to simply as a FIFO) is required to temporarily store the serial data as it is received. A programmable interconnect circuit providing such serializer/deserializer, clock data recovery, and FIFO capabilities is disclosed in “High Speed Interface for a Programmable Interconnect Circuit, U.S. Ser. No. 10/023,226, filed Dec. 14, 2001, the contents of which are hereby incorporated by reference in their entirety.
Problems may arise when incorporating a conventional FIFO into a programmable interconnect circuit. In a conventional FIFO, the outputs are registered. However, a programmable interconnect circuit already possesses I/O cells that also register input and output signals to the device. Should the programmable interconnect circuit be routing serialized data using a conventional FIFO, an unnecessary clock cycle would be consumed by the FIFO's output register to provide an output that in turn will be registered by an I/O cell. In addition, a user may want to route serialized data through the programmable interconnect circuit but use an external FIFO to coordinate the asynchronous clocks. However, should the programmable interconnect circuit possess a conventional FIFO, the registering of its outputs would hinder the use of the external FIFO.
Accordingly, there is a need in the art for improved FIFO designs that will address the problems associated in incorporating a conventional FIFO into a programmable interconnect circuit.
SUMMARY
In accordance with one aspect of the invention, a programmable logic device (PLD) include a plurality of N pins and a corresponding plurality of N registers, wherein each register may store a signal coupled from its corresponding pin according to an internal PLD clock. A first-in-first-out (FIFO) memory within the PLD may store words according to an external write clock and retrieve the stored words according to the internal PLD clock. A subset of the registers may be configured to store, according to a given cycle of the internal PLD clock, the current retrieved word from the FIFO memory.


REFERENCES:
patent: 6011407 (2000-01-01), New
patent: 2003/0052709 (2003-03-01), Venkata et al.

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