Amplifiers – Sum and difference amplifiers
Reexamination Certificate
2003-03-21
2004-08-03
Nguyen, Khanh Van (Department: 2817)
Amplifiers
Sum and difference amplifiers
C330S259000, C330S290000
Reexamination Certificate
active
06771122
ABSTRACT:
RELATED APPLICATIONS
This application claims the priority of Korean Patent Application No. 2002-24485 filed on May 3, 2002 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DC offset compensation, and more particularly, to a DC offset compensation circuit of a closed loop operational amplifier and a method of compensating for DC offset.
2. Description of the Related Art
An operational amplifier is a basic element of an analog circuit. Of the characteristics of the operational amplifier, the input offset voltage is a voltage that is applied to an input node to cause the output voltage to be 0V. The offset voltage can vary, depending on the manufacturing process and the operating temperature. The offset voltage can be classified as a systematic offset voltage and a random offset voltage, according to characteristics of factors that generate it. Systematic offset voltage is determined based on design parameters and can be reduced if the size of a transistor is set so that DC current flows fully through it. The random offset voltage is generated based on manufacturing process parameters, e.g., an error in the size of a transistor, variations in threshold voltage, and the like, and can be mitigated if the size of the transistor is increased.
However, although the operational amplifier is designed using a transistor matching process such that the systematic offset voltage is not generated, the random offset voltage, as stated above, is generated according to the manufacturing process, layout mismatch, and the like. If the closed loop gain of the operational amplifier is greater than “1”, the output DC offset becomes greater by the closed loop gain. One method of removing the DC offset utilizes a high-pass filter (HPF), as shown in
FIG. 1
, in which the settling time becomes longer as the DC voltage of the input signal varies.
FIG. 1
is a block diagram of a closed loop operational amplifier having a conventional DC offset compensation circuit utilizing a high-pass filter (HPF). Referring to
FIG. 1
, a resistor R
1
is connected between an input node to which an input signal Vin is input at a negative input node of a first operational amplifier
11
. A resistor R
2
is connected between the negative input node of the first operational amplifier
11
and an output node of the first operational amplifier
11
. A resistor R
3
is connected between the output node of the first operational
11
and a negative input node of a second operational amplifier
13
. A resistor R
4
is connected between the negative input node of the second operational amplifier
13
and an output node of the second operational amplifier
13
. A reference voltage Vref is input to a positive input node of the first operational amplifier
11
and a positive input node of the second operational amplifier
13
. A DC offset compensation circuit
15
including the HPF is connected to an output node of the second operational amplifier
13
.
It is assumed that a gain of the closed loop operational amplifier is (R
2
/R
1
)*(R
4
/R
3
). Thus, if an input DC offset is distorted by about 10 mV, the output DC offset is distorted by 10 mV*(R
2
/R
1
)*(R
4
/R
3
). In order to prevent the DC offset from varying, in the prior art, the DC offset compensation circuit
15
including the HPF is connected to the output node of the second operational amplifier
13
.
FIG. 2
is a graph illustrating compensation simulation results using the circuit shown in FIG.
1
. As seen in
FIG. 2
, when a DC voltage of the input signal Vin varies from 2.3V to 2.7V, output signal Vout requires a considerable amount of time to reach the desired DC voltage level, i.e., 2.5V. As a result, the output signal Vout does not have a continuous variation in the DC voltage of the input signal Vin. In other words, the settling time of the output signal Vout becomes longer.
SUMMARY OF THE INVENTION
To address the above-described limitations of the conventional embodiments, it is a first object of the present invention to provide a DC offset compensation circuit which is capable of reducing the settling time of an output signal through fast compensation for a DC offset of the output signal, although the DC voltage of the input signal varies in a closed loop operational amplifier.
It is a second object of the present invention to provide a closed loop operational amplifier having such a DC offset compensation circuit.
It is a third object of the present invention to provide a method of compensating for DC offset in which the settling time of an output signal can be reduced through fast compensation for the DC offset of the output signal, although the DC voltage of the input signal varies in a closed loop operational amplifier.
To achieve the first object, there is provided a DC offset compensation circuit of a closed loop operational amplifier having a first closed loop operational amplifier which amplifies an input signal based on a first reference voltage, and a second closed loop operational amplifier which amplifies a signal output from the first closed loop operational amplifier based on a second reference voltage to generate a final output signal. The DC offset compensation circuit includes a buffer, a low-pass filter, and a comparator. The buffer buffers a signal output from the second closed loop operational amplifier. The low-pass filter low-pass filters a signal output from the buffer and detects a DC voltage value of the signal. The comparator compares the DC voltage value with the second reference voltage, generates a compensation voltage based on the compared result, and supplies the compensation voltage as the first reference voltage to the first closed loop operational amplifier.
A cut-off frequency of the low-pass filter varies with a frequency of the input signal. According to a preferred embodiment, the comparator includes an operational amplifier, a first resistor, and a second resistor. The operational amplifier receives the detected DC voltage value at a positive input node. The first resistor is connected between a negative input node of the operational amplifier and the second reference voltage. The second resistor is connected between the negative input node of the operational amplifier and an output node of the operational amplifier.
To achieve the second object, there is provided a closed loop operational amplifier including a first closed loop operational amplifier, a second closed loop operational amplifier, and a DC offset compensation circuit. The first closed loop operational amplifier amplifies an input signal based on a compensation voltage. The second closed loop operational amplifier amplifies a signal output from the first closed loop operational amplifier based on a reference voltage to generate a final output signal. The DC offset compensation circuit receives the final output signal, detects a DC voltage of the final output signal that varies with a variation in a DC voltage of the input signal, and supplies the compensation voltage corresponding to the DC voltage of the final output signal to the first closed loop operational amplifier.
According to a preferred embodiment, the DC offset compensation circuit includes a buffer which buffers the final output signal, a low-pass filter which low-pass filters a signal output from the buffer to detect a DC voltage value of the signal, and a comparator which compares the DC voltage value with the reference voltage and generates the compensation voltage based on the compared result. A cut-off frequency of the low-pass filter varies with a frequency of the input signal. According to the preferred embodiment, the comparator includes an operational amplifier which receives the detected DC voltage value at a positive input node, a first resistor which is connected between a negative input node of the operational amplifier and the reference voltage, and a second resistor which is connected between the negative input node of the op
Jin Woo-kang
Song Moon-sik
Mills & Onello LLP
Nguyen Khanh Van
Samsung Electronics Co,. Ltd.
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