FIFO memory and line buffer

Details FIFO memory and line buffer FIFO memory and line buffer

1992-06-02

1994-06-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523005, 36523008, G11C 700, G11C 1928

Patent

active

053195973

ABSTRACT:
This invention provides a FIFO memory device having a simple circuit structure without using a cache memory, and line buffers used in the FIFO memory device having a simplified circuit structure.
The FIFO memory device comprises a read line buffer (5) having a two-step structure in place of a cache memory which stores and outputs the first data. The read line buffer (5) outputs the data from the memory array (4). Namely, the read line buffer (5) comprises first-step master latch circuits (33) and (34) and a second-step slave latch circuit (37), and the single master latch circuit (33) functions equivalent to the cache memory. In addition, the number of line buffers is reduced by multiplying the selection of memory array (4) bit lines (BL) using transfer gates (11-14).

REFERENCES:
patent: 4715017 (1987-12-01), Iwahashi

Affiliated with

Also associated with

Rating

FIFO memory and line buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIFO memory and line buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO memory and line buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-798760