Field effect transistors having elevated source/drain regions

Details Field effect transistors having elevated source/drain regions Field effect transistors having elevated source/drain regions

2000-10-06

2003-06-17

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000, C257S330000, C438S489000, C438S300000

Reexamination Certificate

active

06580134

ABSTRACT:

RELATED APPLICATIONS
This application is related to Korean Application No. 99-43210, filed Oct. 7, 1999, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and fabrication methods thereof, and more particularly, to field effect transistor (FETs) and fabrication methods for field effect transistors.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuits continues to increase, the size of Field Effect Transistors (FET), such Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), implemented in such integrated circuits may also decrease. However, a decrease in the size of a MOSFET may reduce the MOSFET's channel length. As appreciated by those skilled in the art, a reduction in the MOSFET's channel length may cause a “short channel effect” (SCE) which may increase the likelihood of a phenomenon known as “punch through” between a source and a drain of the MOSFET.
Short channel effects may arise when the depletion region widths of the source and drain junctions become comparable to the channel length. As a result, the potential distribution in the channel may become two-dimensional which can result in large values of sub-threshold current, a decrease in threshold voltage, and/or non-saturation of drain current due to punch through. Punch through may occur when the sum of the source and drain depletion widths exceed the channel length, thereby causing the channel to be punched through (i.e., the depletion region punches through the neutral n-region) when voltage is applied. Thus, since “short channel effects” may complicate device operation and may degrade device performance, it may be desirable to reduce these effects.
In order to reduce the SCE and “punch through”, semiconductor devices have been produced using a technique conventionally known as Selective Epitaxial Growth (SEG). SEG may be used to form an epitaxial layer having an elevated source/drain structure. However, using SEG may result in the formation of a “facet” at the edge of the epitaxial layer. During subsequent ion implantation and thermal treatment, that are used when forming source/drain impurity regions, these facets may cause the electrical characteristics of the resultant semiconductor devices to deteriorate. Problems with the conventional SEG techniques will now be further discussed with reference to FIG.
1
.
FIG. 1
shows a cross-sectional view of an FET having an elevated source/drain structure fabricated using conventional SEG techniques. A gate pattern including a gate oxide film
55
, a gate electrode
57
and gate spacers
61
are formed on an integrated circuit substrate such as a silicon semiconductor substrate
51
in which an isolation film
53
has been formed by trench isolation. An epitaxial layer
59
is then formed by an SEG process on both sides of the gate pattern and on areas of the semiconductor substrate
51
. When ion implantation is performed using the gate pattern as an ion implantation mask, and thermal treatment is performed to activate implanted impurities, an impurity profile
63
is formed in the source/drain region. One problem with this conventional process for fabricating an FET is the formation of a facet A at the edge of the epitaxial layer
59
. Such a facet A may undesirably result the formation of a non-uniform impurity region B in the impurity profile
63
at the source/drain region. As shown in
FIG. 1
, this non-uniform impurity region B has a locally-deep junction which can increase the likelihood of “short channel effects” in the FET which can in turn cause “punch through”. As discussed above, these problems may ultimately degrade the electrical characteristics of the semiconductor device.
One method for fabricating an FET was disclosed in U.S. Pat. No. 4,998,150 to Rodder et al., entitled “RAISED SOURCE/DRAIN TRANSISTOR.” According to this method, a raised source/drain transistor is provided having thick sidewall spacing insulators adjacent the transistor gate. A first sidewall spacer is disposed adjacent thin sidewall spacing insulator and raised source/drain region. A second sidewall spacer is formed at the interface between field insulating region and raised source/drain region. Unfortunately, the area occupied by the source/drain region may be reduced by the area occupied by the additional sidewall spacer which may, in turn, influence the impurity profile that is formed in the source/drain region. Moreover, this method may be complicated since an additional process step for forming the additional sidewall spacer may need to be performed.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention comprise field effect transistors (FETs) that include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. A respective one of the recessed regions is located on a respective opposite side of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film.
Preferably, the elevated source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The elevated source/drain structure adjacent the gate is preferably at least as thick as the elevated source/drain structure remote from the gate. The source/drain structure may have a substantially constant thickness remote from the gate. In other embodiments, the elevated source/drain structure on each of the recessed regions is thicker adjacent the gate than remote from the gate. The elevated source/drain structure preferably increases in thickness towards the gate, and/or can also increase in slope towards the gate. In other words, the elevated source/drain structure preferably extends further away from the floor adjacent the gate than remote from the gate.
Embodiments of the present invention also relate to methods for fabricating a field effect transistor (FET) having an elevated source/drain structure. These embodiments can comprise the steps of: providing an integrated circuit substrate having a surface and a gate on the surface; removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, a respective one of which is located on a respective opposite side of the gate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.
The step of epitaxially growing may comprise growing the layer such that the layer extends from the sidewall of the recessed region. Since the recessed region is defined by a floor and a sidewall, the step of epitaxially growing preferably results in growing the layer such that the layer is free of a facet adjacent the gate. For instance, the step of epitaxially growing may comprise growing the layer such that the epitaxial layer having a first thickness growth rate adjacent the gate and a second thickness growth rate remote from the gate, the second thickness growth rate being greater than the first thickness growth rate. As a result, during the step of epitaxially growing, the layer may be grown such that the layer adjacent the gate is at least as thick as the layer is remote from the gate, and optionally the step of epitaxially growing may comprise growing the layer such that the layer has a substantially constant thickness remote from the gate. The epitaxial layer adjacent the gate may be grown such that the thickness is equal to or greater than the thickness of the epitaxial layer remote from the gate. Preferably, the step of epitaxially growing comprises growing the layer such that the layer

Affiliated with

Also associated with

Rating

Field effect transistors having elevated source/drain regions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Field effect transistors having elevated source/drain regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistors having elevated source/drain regions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3120074