Field effect transistors (FETs) with multiple and/or...

Details Field effect transistors (FETs) with multiple and/or... Field effect transistors (FETs) with multiple and/or...

2007-09-05

2010-10-19

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S595000, C438S655000, C438S683000, C257S384000, C257S408000, C257SE21439

Reexamination Certificate

active

07816219

ABSTRACT:
A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

REFERENCES:
patent: 6063681 (2000-05-01), Son
patent: 6255703 (2001-07-01), Hause et al.
patent: 2002/0008295 (2002-01-01), Yang et al.
patent: 2002/0137268 (2002-09-01), Pellerin et al.
patent: 2003/0183881 (2003-10-01), Lee et al.

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