Field effect transistor with improved isolation structures

Details Field effect transistor with improved isolation structures Field effect transistor with improved isolation structures

2001-10-25

2004-05-04

Eckert, George (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S420000, C438S449000, C438S451000

Reexamination Certificate

active

06730569

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates, in general, to the field of electronic devices and, more particularly, to an improved field effect transistor having improved isolation structures and a method for forming the same.
BACKGROUND OF THE INVENTION
The ability to deliver higher performance for less cost in electronic devices depends on the capability of the electronic device designer to construct more active devices in a given surface area on a semiconductor substrate. As active devices are placed closer and closer to one another, the importance of isolation structures between the active devices becomes more critical. Isolation structures typically involve the formation of field oxides and implanted regions and serve to prevent the formation of parasitic devices formed from implanted regions of neighboring structures.
As the active devices themselves are placed closer and closer to the isolation structures however, a new problem has arisen. An active device can be placed in an operational mode so that a breakdown condition is reached resulting in a formation of a parasitic current path through the isolation structure itself. This condition limits the operational characteristics of field effect devices and other active devices.
Accordingly, a need has arisen for an improved field effect transistor and isolation structure architecture that prevents the formation of such parasitic current paths.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, an improved field effect transistor and isolation structure architectures are provided that substantially eliminate or reduce problems associated with prior art structures including the formation of unwanted parasitic current paths which serve to limit the operational characteristics of the field effect device.
In accordance with one embodiment of the present invention, a method for forming a field effect device is presented which comprises covering an active region of a semiconductor layer with a first mask layer. A first channel stop implant process is then used to form first channel stop regions abutting opposing sides of the active region. A second mask layer is then formed covering the first mask layer and portions of the outer surface of the active region and the first channel stop region on opposing sides of the first mask layer. A second channel stop implant is then performed to form second channel stop regions disposed in the outer surface of the semiconductor layer proximate the outer boundaries of the second mask layer.
According to an alternate embodiment of the present invention, the second mask layer can then be removed and field oxide structures can be created while the first mask layer is still in place.
The present invention enjoys the important technical advantage that it allows for the creation of effective channel stop isolation structures but provides for enough spacing between the isolation structures and the active region to prevent the onset of parasitic currents.


REFERENCES:
patent: 4945066 (1990-07-01), Kang et al.
patent: 5242849 (1993-09-01), Sato
patent: 5432107 (1995-07-01), Uno et al.
patent: 5786265 (1998-07-01), Hwang et al.
patent: 5841163 (1998-11-01), Joo et al.

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