Field effect transistor with electroplated metal gate

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27060

Reexamination Certificate

active

07112851

ABSTRACT:
Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

REFERENCES:
patent: 6188120 (2001-02-01), Andricacos et al.
patent: 6255187 (2001-07-01), Horii
patent: 6391773 (2002-05-01), Andricacos et al.
patent: 6686282 (2004-02-01), Simpson et al.
patent: 6777317 (2004-08-01), Seibel et al.
patent: 6873048 (2005-03-01), Gao et al.
Misra, et al., “Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si—CMOS”,IEEE Electron Device Letters23 354 (2002).
Zhong, et al., “Properties of Ru—Ta alloys as Gate Electrodes for NMOS and PMOS Silicon Devices”,IDEM01 467 (2001).

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