Field effect transistor with electrically induced drain and...

Details Field effect transistor with electrically induced drain and... Field effect transistor with electrically induced drain and...

2000-07-10

2002-02-19

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S389000

Reexamination Certificate

active

06348387

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with electrically induced drain and source extensions for minimizing short channel effects in the field effect transistor having scaled-down dimensions of tens of nanometers.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. To prevent short channel effects as the dimensions of the MOSFET
100
are further scaled down, shallower junctions for the drain and source extensions
104
and
106
are desired. Conventionally, the drain and source extensions
104
and
106
are formed by implantation of a dopant into the semiconductor substrate
102
. However, the shallow depth of the junctions for the drain and source extensions
104
and
106
may be limited when the implanted dopant forms such junctions because of thermal processes which heat up the semiconductor substrate
102
. The dopant within the junctions for the drain and source extensions
104
and
106
thermally drift during such thermal processes to increase the depth of such junctions.
Thus, a mechanism is desired for fabricating junctions for the drain and source extensions that remain shallow with thermal processes during fabrication of the integrated circuit having the MOSFET.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, conductive spacers are formed on the sidewalls of a gate structure of a MOSFET for forming electrically induced drain and source extensions. Such electrically induced drain and source extensions remain shallow even with thermal processes during fabrication of the MOSFET.
In one embodiment of the present invention, for fabricating a field effect transistor within an active device area of a semiconductor substrate, a gate dielectric is formed on the active device area of the semiconductor substrate, and a gate structure is formed on the gate dielectric with the gate structure being comprised of a first conductive material. A drain spacer comprised of a second conductive material is formed on a first sidewall of the gate structure, and a first liner dielectric is formed between the drain spacer and the first sidewall of the gate structure and between the drain spacer and the semiconductor substrate. A source spacer comprised of the second conductive material is formed on a second sidewall of the gate structure, and a second liner dielectric is formed between the source spacer and the second sidewall of the gate structure and between the source spacer and the semiconductor substrate.
Application of at least a drain threshold voltage on the drain spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the first liner dielectric to form a drain extension of the field effect transistor. Similarly, application of at least a source threshold voltage on the source spacer with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the second liner dielectric to form a source extension of the field effect transistor. In addition, application of at least a gate threshold voltage on the gate structure with respect to the semiconductor substrate induces charge accumulation in the semiconductor substrate under the gate dielectric to turn on the field effect transistor.
The present invention may be used to particular advantage when the first conductive material of the gate structure is polysilicon and germanium with a germanium content in a range of from about 50% to about 80%, and when the second conductive material of the drain and source spacers is polysilicon such that the gate threshold voltage is greater than the drain and source threshold voltages. In that case, a gate silicide is formed with the first conductive material of the gate structure and with the second conductive material of the drain and source spacers such that the gate structure and the drain and source spacers are electrically connected. Application of a predetermined turn-off voltage that is less than the gate threshold voltage and greater than the drain and source threshold voltages on the gate silicide forms the drain extension and the source extension when the field effect transistor is turned off.
In this manner, the drain extension and the source extension of the field effect transistor are electrically induced and have a shallow depth of from about 5 Å (angstroms) to about 15 Å (angstroms). Because the drain extension and the source extension of the field effect transistor are electrically induced, the drain extension and the source extension are shallow regardless of thermal processes used for fabrication of the integrated circuit having the field effect transistor.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.


REFERENCES:
patent: 4868617 (1989-09-01), Chiao et al.
patent: 6232166 (2001-05-01), Ju et al.
patent: 6300205 (2001-10-01), Fulford et al.

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