Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-07
2004-08-24
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S527000
Reexamination Certificate
active
06780722
ABSTRACT:
The invention relates to a transistor formed on an insulating layer, especially a silicon-on-insulator transistor and method of its manufacture, and in particular to a method of improving ruggedness.
An example of a Silicon-on-Insulator design is shown in
FIG. 1. A
buried oxide layer
4
is formed on substrate
2
, and an active semiconductor layer
6
on the buried oxide layer
4
. An n-type drain region
8
, p-type body region
10
and source region
12
are defined in the active semiconductor layer
6
. The drain region
8
is divided into a relatively lightly doped drift region
14
and a heavily doped contact region
16
. A polysilicon gate
18
is provided above the active layer
6
separated from the active layer
6
by a gate insulator
20
. A source metallisation
22
contacts the source and a drain metallisation
24
contacts the drain.
A problem in FETs is the existence of parasitic bipolar transistors, formed from the source, body and drain regions. Referring to
FIG. 1
, the source
12
, body
10
and drain
8
form the emitter, base and collector of the parasitic transistor. By shorting the source
12
and body
10
, together, for example by connecting both to the source metallisation
22
as shown, the emitter and base of the parasitic transistor are shorted together which suppresses the parasitic bipolar transistor.
However, under high current conditions sufficient current may flow through the body region
10
past the source region to the metallisation that a voltage is dropped in the body region under the source region
12
between lower corners
26
,
28
of the source region. If this voltage is high enough, the voltage is sufficient to forward bias the parasitic transistor.
High current may occur under conditions of unclamped inductive turn-off, or very high voltage rates of change. Resistance to turning on of the parasitic bipolar transistor in these conditions is known as “ruggedness”.
Even if failure does not occur, the voltage needed to trigger the parasitic in subsequent events will be reduced by the high temperatures, leading to a more rapid turn on of the parasitic transistor. After a number of events the device may fail as the hot spot gets hotter and hotter in each event.
An p-type implant
30
may be provided in the upper part of the body region
10
adjacent to the source region
12
. This can provide a lower resistance path, reducing the voltage drop between corners
26
,
28
in high current conditions and so reducing the propensity of the parasitic transistor to turn on.
An alternative example of a FET is described in WO 96/07200 to International Rectifier Corporation in which the whole p-type body and the n-type source are deposited through a single mask hole.
Unfortunately, in this prior design the p-type implant affects the doping of the body region just under the gate
18
, and accordingly makes it very difficult to arrange suitable channel doping. WO 96/07200 states that “proper selection of diffusion parameters will prevent the P+ doping from reaching the surface channel regions in sufficient quantity to substantially change the threshold voltage”, but does not appear to provide detailed instructions of how the diffusion parameters are to be selected. Indeed, it is hard to see how it is possible to provide highly doped p+ and lower doped p regions from a single implant and diffusion without also having a very uneven doping concentration along the channel. Process variation would result in threshold voltage variation and it is hard to see how these could be compensated for.
Accordingly, it would be beneficial to improve the ruggedness of a field effect transistor without significantly affecting the channel doping or greatly increasing process complexity.
According to the invention there is provided a method of manufacturing a field effect transistor including: providing body and drain semiconductor regions laterally adjacent on an insulating layer; defining a source region mask having openings over part of the body region; implanting through the openings an implant region of the same conductivity type as the body region and more highly doped than the body region; implanting through the openings a source region of opposite conductivity type to the body region at the surface of the body region laterally aligned with the implant region; and activating the source and implant regions.
The invention also relates to a field effect transistor comprising an insulating layer; an active semiconductor layer over the insulating layer, the active semiconductor layer including a body semiconductor region laterally of a drain semiconductor region; a source region of opposite conductivity type to body region implanted at the surface of the body region; and an implant region doped to have the same conductivity type as the body region but higher doping concentration substantially laterally aligned with the source region and extending in the vertical direction below the source region.
The implant region under the source region is highly doped and accordingly reduces voltage drop caused by any lateral current flowing under the source region in the body region. The pn junction between source and body is accordingly less susceptible to becoming strongly forward biased, whereby the ruggedness of the transistor is improved.
The inventors have realised that by defining the bulk of the body region including the channel in a first step and the implant region using the source mask in a second step it is possible to get good ruggedness protection without the need for excessive numbers of masks and corresponding alignment steps.
The process has significant advantages over the prior p-type implant approach illustrated in FIG.
1
. For example, it is possible to obtain a highly p-type doped implant region adjacent to the source region without upsetting the doping in the channel region and thereby degrading the threshold voltage. The channel doping can be selected as in a conventional device by selecting the doping of the bulk body region without needing to arrange in the same step that a highly doped p-type region is provided in the correct location.
The implant region can be implanted using the same mask as the source metallisation, avoiding the need for a separate mask step.
It is possible to heat up and activate the implant region.
Moreover, by using the approach of the invention it is possible to provide an implant region extending from the insulating layer to the source region. This means that all of the breakdown current under the source, which is largely lateral in SOI devices, passes through the high doping density and accordingly low resistance implant region. This reduces the chance of generating large voltages that may turn on the parasitic bipolar transistor. Referring to prior art
FIG. 1
breakdown may occur at corner
32
of implant
30
. By extending the implant region all the way from the insulating layer to the source such corners in the implant region are avoided.
It is preferred that the source implant and implant region are activated together after they are both formed. This avoids any need for a separate activation step to activate the p implant, and also avoids increasing the thermal budget of the process, i.e. avoids adding extra heating steps.
It is thus preferred that the activation step does not cause significant diffusion of the p implant. However, in alterative embodiments the activation step may be a diffusion step which may be beneficial to round off the edges of the implant region, and possibly also the source region.
REFERENCES:
patent: 4677735 (1987-07-01), Malhi
patent: 5268586 (1993-12-01), Mukherjee et al.
patent: 2003/0008465 (2003-01-01), Chen
patent: 0638938 (1995-02-01), None
patent: WO9607200 (1996-07-01), None
“SOI LIGBT Devices with a Dual P-Well Implant for Improved Latching Characteristics”, by D.R. Disney et al., May, 1993, pp. 254-258.
Fahmy Wael
Koninklijke Philips Electronics , N.V.
Peralta Ginette
Waxler Aaron
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