Field effect transistor having reduced contact resistance...

Details Field effect transistor having reduced contact resistance... Field effect transistor having reduced contact resistance...

2010-03-12

2011-10-18

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S285000, C438S604000, C257SE21403

Reexamination Certificate

active

08039329

ABSTRACT:
A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1−yN (wherein 0<x≦1, 0≦y<1 and 0<x+y≦1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.

REFERENCES:
patent: 7217960 (2007-05-01), Ueno et al.
patent: 2004/0079959 (2004-04-01), Udagawa
patent: 2005/0006664 (2005-01-01), Inoue et al.
patent: 2005/0156188 (2005-07-01), Ro et al.
patent: 2006/0180831 (2006-08-01), Nakazawa et al.
patent: 2006/0281284 (2006-12-01), Harris et al.
T. Mureta et al., âSource Resistance Reduction of AIGaN-GaN HFETs with Novel Superlattice Cap Layer,â IEEE Transactions on Electron Devices, vol. 52, pp. 1042-1047, 2005.

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