Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-11
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06300182
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to field effect transistors having scaled-down dimensions, and more particularly, to a field effect transistor having dual gates with asymmetrical doping on sides of a semiconductor pillar in SOI (semiconductor on insulator) technology for reducing the threshold voltage of the field effect transistor.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET
100
. Short-channel effects that result due to the short length of the channel between the drain extension
104
and the source extension
106
of the MOSFET
100
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET
100
become difficult to control with bias on the gate electrode
118
with short-channel effects which may severely degrade the performance of the MOSFET.
Referring to
FIG. 2
, to enhance the control of electrical characteristics of a MOSFET
200
, a three-sided gate electrode
202
is formed to surround a pillar
204
of semiconductor material for the MOSFET
200
formed with SOI (semiconductor on insulator) technology.
FIG. 3
shows the cross sectional view of the three-sided gate electrode
202
across line A—A in FIG.
2
. The pillar
204
of semiconductor material is formed on a layer of buried insulating material
206
on a semiconductor substrate
208
in SOI (semiconductor on insulator) technology, as known to one of ordinary skill in the art of integrated circuit fabrication. Typically, the semiconductor substrate
208
and the pillar
204
are comprised of silicon, and the three-sided gate electrode
202
is comprised of polysilicon. In addition, the layer of buried insulating material
206
is comprised of silicon dioxide (SiO
2
).
A three-sided gate dielectric
210
is formed between the pillar
204
and the three sided gate electrode
202
. The three-sided gate dielectric
210
is comprised of one of silicon dioxide (SiO
2
), silicon nitride (Si3N4), or a dielectric material such as a metal oxide with a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
).
A drain and source dopant is implanted into the pillar
204
at a first side of the three-sided gate electrode
202
to form a drain
212
of the MOSFET
200
and at a second side of the three-sided gate electrode
202
to form a source
214
of the MOSFET
200
. A drain contact pad
216
is formed to provide connection to the drain
212
of the MOSFET
200
, and a source contact pad
218
is formed to provide connection to the source
214
of the MOSFET
200
.
Referring to
FIGS. 2 and 3
, the channel region of the MOSFET
200
is the gate length of the pillar
204
between the drain
212
and the source
214
and covered by the three-sided gate electrode
202
. Because charge accumulation within such a channel region is controlled by bias on the gate electrode
202
on three surfaces of the pillar (instead of just the one top surface of the semiconductor substrate
102
in the conventional MOSFET of FIG.
1
), electrical characteristics of the MOSFET
200
formed with SOI technology is more controllable to compensate for short-channel effects of the MOSFET
200
.
Referring to
FIGS. 2 and 3
, the width of the pillar
204
along the dimension of the dashed line A—A in
FIG. 2
is relatively small in a range of from about 100 Å (angstroms) to about 250 Å (angstroms). Thus, the channel region of the MOSFET
200
is fully depleted, and the threshold voltage
200
of the MOSFET is substantially determined by the doping of the gate electrode
202
. In the prior art, the gate electrode
202
is evenly doped with a same gate dopant, such as an N-type dopant (i.e., phosphorous or arsenic, for example) throughout the gate electrode
202
including at the two side surfaces of the pillar
204
. Such an evenly distributed dopant however results in a relatively high threshold voltage (greater than 0.6 Volts for example) of the MOSFET
200
. However, a lower threshold voltage may be desired for the MOSFET
200
having scaled down dimensions and for low power applications.
Thus, a mechanism is desired for lowering the threshold voltage of a MOSFET formed from a semiconductor pillar in SOI technology.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, dual gates of a field effect transistor formed by gate electrode material deposited at two side surfaces of a semiconductor pillar are asymmetrically doped with different types of gate dopant to lower the threshold voltage of the MOSFET.
In one embodiment of the present invention, for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface, a left side surface, a right side surface, a front side surface, and a back side surface, and the pillar has a width and a length. A dielectric structure comprised of a hardmask dielectric material is formed on the top surface of the pillar. A first gate dielectric is formed on the left side surface of the pillar, and a second gate dielectric is formed on the right side surface of the pillar, along a gate length of the length of the pillar. A gate electrode material
Advanced Micro Devices , Inc.
Choi Monica H.
Hoang Quoc
Nelms David
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