Field effect transistor having doped gate with prevention of...

Details Field effect transistor having doped gate with prevention of... Field effect transistor having doped gate with prevention of...

2001-03-15

2002-08-13

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S146000, C438S163000, C438S291000, C257S412000

Reexamination Certificate

active

06432763

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a field effect transistor having a doped gate electrode, such as a silicon germanium (SiGe) gate electrode for example, with prevention of contamination of an implantation chamber from the bombardment of the implantation ions with the gate electrode.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET
100
. Short-channel effects that result due to the short length of the channel between the drain extension
104
and the source extension
106
of the MOSFET
100
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET
100
become difficult to control with bias on the gate electrode
118
with short-channel effects which may severely degrade the performance of the MOSFET.
As the dimensions of the MOSFET
100
are further scaled down to tens of nanometers, short channel effects are more likely to disadvantageously affect the operation of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to
FIG. 1
, to prevent short channel effects as the dimensions of the MOSFET
100
are further scaled down, halo regions
105
and
107
are formed by the drain extension junction
104
and the source extension junction
106
in the semiconductor substrate
102
. A drain halo region
105
is formed by the drain extension junction
104
, and a source halo region
107
is formed by the source extension junction
106
.
The halo regions
105
and
107
are implanted with a halo dopant that is opposite in type to the dopant within the drain and source extension junctions
104
and
106
. For example, when the drain and source extension junctions
104
and
106
are implanted with an N-type dopant for an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions
105
and
107
are implanted with a P-type dopant for preventing short channel effects of the NMOSFET. On the other hand, when the drain and source extension junctions
104
and
106
are implanted with a P-type dopant for a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor), the halo regions
105
and
107
are implanted with an N-type dopant for preventing short channel effects of the PMOSFET. Such halo regions
105
and
107
are known to one of ordinary skill in the art of integrated circuit fabrication.
As the dimensions, including the thickness (i.e., the height), of the gate electrode
118
are further scaled down, resistance of the gate electrode
118
may limit the device speed of the MOSFET
100
. To minimize resistance of the gate electrode, the gate electrode
118
is formed with a doped semiconductor material such as silicon doped with germanium instead of just polysilicon. For example, the gate electrode
118
is comprised of silicon germanium (SiGe) having a germanium concentration in a range of from about
10
atomic percent to about 60 atomic percent.
Such a silicon germanium gate electrode
118
is advantageous because an N-type or P-type dopant has a higher activation rate within silicon germanium (than in just polysilicon), as known to one of ordinary skill in the art of integrated circuit fabrication, to minimize the resistance of the silicon germanium gate electrode
118
. In addition, a silicon germanium gate electrode
118
effectively suppresses diffusion of an N-type or P-type dopant, such as boron for example, from the silicon germanium gate electrode
118
into the gate dielectric
116
and the semiconductor substrate
102
. Such diffusion of dopant from the gate electrode
118
into the gate dielectric
116
and the semiconductor substrate
102
disadvantageously affects the threshold voltage of the MOSFET
100
.
Referring to
FIG. 2
, to further enhance the control of the electrical characteristics of a MOSFET as the dimensions of the MOSFET are scaled down, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
150
is fabricate in SOI (semiconductor on insulator) technology. In SOI technology, a layer of buried insulating material
132
is deposited on the semiconductor substrate
102
. The layer of buried insulating material
132
is typically comprised of silicon dioxide (SiO
2
) when the semiconductor substrate
102
is comprised of silicon. In addition, a thin silicon film
134
is deposited on the layer of buried insulating material
132
.
A gate dielectric
136
and a gate electrode
138
are formed on the thin silicon film
134
. A drain and source dopant is implanted into exposed regions of the thin silicon film
134
to form a drain
142
and a source
144
of the MOSFET
150
. A channel region of the MOSFET
150
is the portion of the thin silicon film
134
disposed between the drain
142
and the source
144
and disposed below the gate dielectric
136
. The silicon film
134
is relatively thin having a thickness in a range of from about 5 nanometers to about 20 nanometers for example. Thus, the channel region of the MOSFET
150
is fully depleted during operation of the MOSFET
150
with improved control of electrical characteristics of the MOSFET
150
, as known to one of ordinary skill in the art of integr

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