Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-30
2002-06-11
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S362000, C438S164000
Reexamination Certificate
active
06403427
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to integrated circuit devices and their fabrication, and more particularly, to integrated circuit transistors and methods for their fabrication.
BACKGROUND OF THE INVENTION
A number of potential problems are caused by the high circuit element density of today's integrated circuits. For example, densely packed field-effect transistors have relatively short channel lengths, resulting in increased potential for punchthrough effects. Also, the correspondingly shallow drain and source junction depths can result in junction spiking, in which metallization layers penetrate drain and source diffusions. The short channel lengths also result in higher electric field strengths, which in turn cause deleterious hot carier effects. Reduced device geometries increase capacitive coupling between source/drain regions and the body of the transistor, resulting in degraded device performance and signal transmission characteristics. In the case of CMOS technology, parasitic thyristors and associated latchup effects arise. These and other fundamental problems must be addressed by the circuit designer and process engineer.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a transistor is provided having first, second, and third semiconductor regions. The first region is a substantially monocrystalline semiconductor region of a first conductivity type protruding from a body region of a semiconductor substrate. A dielectric region overlies the body region and substantially laterally adjoins the first region. The second and third regions are semiconductor regions of a second conductivity type overlying the dielectric region and substantially laterally adjoining the first region. The second and third regions include both substantially polycrystalline and substantially monocrystalline semiconductor material.
In another embodiment, a field-effect transistor is provided. The transistor includes a monocrystalline semiconductor body region, with a monocrystalline semiconductor channel region extending therefrom. First and second semiconductor source/drain regions laterally adjoin the channel region and are substantially electrically isolated from the body region. The transistor may include a dielectric region underlying the source/drain regions to electrically isolate these regions from the body region. The source/drain regions may include substantially polycrystalline semiconductor material and substantially monocrystalline semiconductor material. The transistor may include a conductive gate electrode region proximate to and electrically coupled with the channel region. The transistor may further include a dielectric region adjacent the channel region, with the conductive gate electrode region adjacent to the dielectric region and capacitively coupled with the channel region.
In accordance with an embodiment of the present invention, a method of fabricating an integrated circuit device is provided. The method includes forming a substantially monocrystalline semiconductor substrate having a body region and a protruding region extending from the body region. An electrical isolation region is then formed which overlies the body region. An additional semiconductor region is formed which overlies the isolation region and laterally adjoins the protruding region. Forming the electrical isolation region may include forming a dielectric layer overlying the body region and laterally adjacent to the protruding region. The formation of the additional semiconductor region may include formation of a substantially polycrystalline semiconductor layer or may include formation of a substantially monocrystalline semiconductor epitaxial region. The formation of the body region and the protruding region may be accomplished by selectively removing portions of the semiconductor substrate. The removal of portions of the semiconductor substrate may include selective oxidation of portions of the semiconductor substrate.
REFERENCES:
patent: 3617822 (1971-11-01), Kobayashi et al.
patent: 4017341 (1977-04-01), Suzuki et al.
patent: 4041518 (1977-08-01), Shimizu et al.
patent: 4214918 (1980-07-01), Gat et al.
patent: 4353085 (1982-10-01), Sakurai
patent: 4477310 (1984-10-01), Park et al.
patent: 4486266 (1984-12-01), Yamaguchi
patent: 4487639 (1984-12-01), Lam et al.
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4609407 (1986-09-01), Masao et al.
patent: 4651408 (1987-03-01), MacElwee et al.
patent: 4763183 (1988-08-01), Ng et al.
patent: 4862232 (1989-08-01), Lee
patent: 4874716 (1989-10-01), Rao
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4914053 (1990-04-01), Matyi et al.
patent: 4916508 (1990-04-01), Tsukamoto et al.
patent: 4966861 (1990-10-01), Mieno et al.
patent: 5106772 (1992-04-01), Lai
patent: 5110757 (1992-05-01), Arst et al.
patent: 5172203 (1992-12-01), Hayashi
patent: 5213991 (1993-05-01), Inokawa et al.
patent: 5338697 (1994-08-01), Aoki et al.
patent: 5347151 (1994-09-01), Shimizu et al.
patent: 5422303 (1995-06-01), Klose et al.
patent: 5498567 (1996-03-01), Klose et al.
patent: 5583067 (1996-12-01), Sanchez
patent: 5668025 (1997-09-01), Banchard
patent: 5970367 (1999-10-01), Wanlass
patent: 0 267 081 (1988-05-01), None
patent: 56-115557 (1981-09-01), None
Carlson David V.
STMicroelectronics Inc.
Trinh (Vikki) Hoa
Weiss Howard
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