Field effect transistor having a floating gate

Details Field effect transistor having a floating gate Field effect transistor having a floating gate

2000-04-24

2001-06-12

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S261000

Reexamination Certificate

active

06245613

ABSTRACT:

TECHNICAL FIELD
The present invention is concerned with a field effect transistor (FET) having a floating gate and especially flash memory cell structures exhibiting high programming efficiency. Furthermore, the present invention is concerned with a process for fabricating the FET structure of the present invention, and is especially concerned with a process for creating a split gate flash memory cell wherein the floating gate is recessed into the silicon substrate.
BACKGROUND OF INVENTION
Field effect transistors (FETs) employing a so-called “floating gate” along with a control gate are well known. The floating gate differs from a control gate in that it has no direct electrical connection to any external component and is surrounded by isolation on all sides. The presence of the control gate enables the device to function as a regular FET, while the floating gate collects and stores injected electrons or holes. The floating gate provides a method for changing the threshold voltage needed to pass a charge from the source to the drain. The presence of the control gate adds control to the injection of charges into and out of the floating gate, and thus enables the device to function as an electrically reprogrammable memory device.
Source-side injection flash cells or split gate flash cells are commonly used as embedded flash memories. In a split gate cell, the floating gate overlies only a portion of the channel and the control gate overlies both the floating gate and the remainder of the channel. In other words, there are two transistors in series between a source and a drain. One relatively popular flash cell employs oxidized polysilicon to create sharp points in the polysilicon in order to enhance the electric field. This in turn allows erasure at lower voltages and provides for thicker dielectric layers between the floating gate and the control gate. The commonly used process for fabricating such cells is referred to as localized oxidation of silicon (LOCOS) process over the floating gate polysilicon to form an insulator cap along with sharp points on the floating gate. The LOCOS process results in bird's beak creating the sharp points.
Nevertheless, the existing flash memory cells exhibit two major shortcomings which are high programming voltage required and non-planar cell topography due to the presence of the floating gate.
In order to inject electrons into the floating gate, either by hot electron or electron tunnelling (Fowler-Nordheim or F-N tunnelling), a high vertical electrical field must be induced. For instance, typically more than about 10 volts of voltage difference is needed between the control gate and source, drain or substrate. For example, with a prior art configuration utilizing source-side hot electron injection, the required programming voltage is 10 V. This split gate flash memory cell as shown in
FIG. 1
has a floating gate on top of the silicon surface that is typical of most of the conventional structures. However, incorporating this technology into a logic application presents problems for metallization due to the topography, especially when wiring dimensions become less than 0.25 microns. Lithographic patterning and reactive ion metal etching both are quite difficult to perform on a non-planar gate surface.
SUMMARY OF INVENTION
The present invention is concerned with a new FET structure that addresses problems in the prior art concerning the cell topography and high programming voltage requirements. According to the present invention, a new structure is provided whereby the floating gate is recessed into the semiconductor substrate. The top of the floating gate is planar with or recessed with respect to the original semiconductor surface.
More particularly, the present invention is concerned with a field effect transistor which comprises a semiconductor substrate that comprises a first doped source region and a second doped drain region separated by a channel region. A conductive floating gate is formed over a first portion of the channel region adjacent to the first doped source region and recessed into the semiconductor substrate and being separated from the first portion of the channel region by a first insulation layer. A conductive control gate is formed substantially over but electrically isolated from the floating gate and is formed over essentially the entire channel region including that portion not located beneath the floating gate. In addition, the present invention is concerned with a process for fabricating the above-described field effect transistor. In particular, the above-described field effect transistor can be fabricated by forming a recess in a semiconductor substrate and providing a floating gate insulating layer on the surface of the recess. Polycrystalline silicon is then deposited in the recess and oxidized leaving a portion of its lower area unoxidized to serve as the floating gate. Shallow trench isolation is then formed. Control gate isolation, control gate, and source and drain regions are provided.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.


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