Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-18
2003-04-01
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000
Reexamination Certificate
active
06541818
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to field-effect transistors with trench-shaped gate electrodes, in which configuration it can be provided that a cell pattern of the transistors is produced by mutually intersecting gate trenches. Mutually intersecting trenches are patterns in which either largely continuous trenches intersect at a point of intersection or trenches are connected to one another at a particular angle, for example at a right angle, at one of their end points. The transistors can be constructed, for example, as MOSFET transistors and as IGBT transistors.
From the prior art it is known, for example from publication EP 0 847 090 or from publication GB 2 314 206, to form a cell pattern of transistors by mutually intersecting trenches. The problem in this configuration is the areas at the corners of the cells at which two trenches meet. Since the doped areas in these corners have two boundary faces to which the dopant can diffuse out, a lower concentration of the dopant is produced in the corners of the cells than in the remaining doped areas of the cell. In addition, the cell corners typically form areas of particularly high electrical field strength. The consequence is that breakdown currents start undesirably early especially in the cell corners or the threshold voltage of the transistor is lower in these areas than in the remaining areas and also may not have adequate long-term stability.
It is, therefore, desirable to avoid the formation of a channel region in the corners of transistor cells. To this end, a configuration is known from U.S. Pat. No. 5,468,982 in which the source region does not extend into the corners of the transistor cell. This can be achieved by masking the cell corners during the production of the source region. However, the disadvantageous factor in this is that an additional masking step becomes necessary for masking the cell corners.
A further problem with the transistor configurations is to achieve resistance to latch-up and short circuits. One possibility for this consists in limiting the maximum current occurring to a value at which the component can still be reliably switched off by using an additional circuit. This is described, for example, in Z. J. Shen and S. P. Robb: A New Current Limit Circuit for Smart Discrete Devices, ISPSD '98, Kyoto 1998, pp. 355-358. However, this measure requires considerable additional circuit expenditure and promotes the occurrence of oscillations.
It is described in U.S. Pat. No. 4,994,871 that the switchable current can be increased in a trench IGBT having additional p-base regions without a source or with a partially cut out source. The disadvantageous factor here is the extracting effect of the additional p regions which, in their conducting state, reduce the carrier flooding and thus increase the forward voltage.
U.S. Pat. No. 4,767,722 points out that the latch-up resistance of a trench-type IGBT can be increased by narrow source regions and thus a reduced lateral base resistance below the source.
A very small distance between adjacent gate trenches, and thus a very high switchable current, is achieved in publication EP 0 755 076. In this configuration, the connection of the p-base region to the contact is conveyed by a p region which is doped more than the source and is diffused in to a lesser depth. However, such an IGBT still needs current limiting since the great channel width allows a short circuit current which is much too great and which would lead to thermal destruction of the component within a very short time.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a field-effect transistor configuration and a method for producing the configuration which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object to provide such a field-effect transistor configuration in which the problems of trench-shaped gate electrodes are largely prevented.
With the foregoing and other objects in view there is provided, in accordance with the invention, a field-effect transistor configuration with a trench-shaped gate electrode. The configuration includes: a substrate region having a first surface and being of a first conduction type; at least one trench formed in the substrate and extending from the first surface, the at least one trench defining walls; an insulation layer covering the walls of the at least one trench; a conductive material filling the trench and forming a gate electrode; a source region configured along the trench and extending into the substrate from the first surface of the substrate, the source region being of the first conduction type; a body region extending underneath the source region and adjoining the trench, the body region being of a second conduction type that is opposite the first conduction type; and a drain region adjoining the body region, the drain region being of the first conduction type. The body region includes at least one highly doped region and remaining areas. The highly doped region is of the second conduction type and has a doping concentration that is higher than that in the remaining areas. The highly doped region is configured at least partially below the source region and adjoins the source region. The at least one highly doped region, at least partially, adjoins the trench. The remaining areas of the body region have a starting voltage. The highly doped region has a starting voltage is that higher than the starting voltage in the remaining areas of the body region.
A first embodiment of the invention relates to a field-effect transistor configuration having a trench-shaped gate electrode which extends in a substrate region of the first type of conduction, a source region of the first type of conduction being configured along the entire trench and underneath the source region, a body region of the second type of conduction being provided which adjoins the source region and the trench. However, it is not necessary that the entire body region is covered by the source region in this configuration.
Preferably, only the part of the body region adjoining the trench is covered by the source region.
In accordance with an important feature of the invention, a highly doped region of the second type of conduction is provided in the body region, is configured at least partially below the source region and adjoins the source region in the vertical direction, and at least partially adjoins the trench in the lateral direction. Thus, the highly doped region does not need to be configured exclusively below the source region. Instead, it can be provided that certain parts of the highly doped region extend under the source region but the remaining area of the highly doped region is configured in those areas of the body region which are not covered by a source region. The highly doped region preferably does not adjoin the trench, in which the gate electrode is formed, along its entire outer edge but only in certain part areas.
It is known that the starting voltage depends on the doping concentration in the channel region which is formed at the boundary of the body region to the gate trench. Thus, the highly doped regions of the second type of conduction in the body region lead to a much higher starting voltage in the areas in which the highly doped regions adjoin the gate trench than in the remaining body region. If a voltage that is always lower than this increased starting voltage is applied to the component, no channel can be formed in the areas in which the highly doped regions adjoin the gate trench. This enables the formation of a channel in the usual operating range of the field-effect transistor only in the remaining body region but not in the area of the highly doped regions. This enables regions of the transistor configuration which are particularly at risk to be closed down. Such regions which are particularly at risk are, for example in the case of a transistor cell, the corners of the cell and/or the areas o
Pfirsch Frank
Schäffer Carsten
Greenberg Laurence A.
Infineon - Technologies AG
Lebentritt Michael S.
Locher Ralph E.
Smith Brad
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