Field effect transistor array including doped two-cell isolation

Details Field effect transistor array including doped two-cell isolation Field effect transistor array including doped two-cell isolation

1998-04-16

2000-03-28

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257202, 257204, 257371, 257372, 257373, 257901, 257909, H01L 2710

Patent

active

060435224

ABSTRACT:
A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

REFERENCES:
patent: 3648130 (1972-03-01), Castrucci et al.
patent: 4661815 (1987-04-01), Takayama et al.
patent: 5723875 (1998-03-01), Abe et al.

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