Field effect transistor and method of manufacturing same

Details Field effect transistor and method of manufacturing same Field effect transistor and method of manufacturing same

2000-07-31

2002-11-05

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S586000, C438S655000, C438S664000, C438S595000

Reexamination Certificate

active

06475844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect transistor (referred to hereinafter as a-MOSFET) subjected to a silicidation process and a method of manufacturing the same.
2. Description of the Background Art
In the past, logic devices such as microprocessors and memory devices represented by a DRAM have been manufactured separately. In recent years, however, semiconductor devices have been more highly integrated, and such separately manufactured logic and memory devices have accordingly been mounted in a single chip (referred to as a hybrid logic-memory device).
Each of the logic and memory devices included in the hybrid logic-memory device comprises transistors. Most of the transistors in either device are MOSFETs. However, there is a difference in required characteristics between MOSFETs constituting a logic circuit and MOSFETs constituting a memory device. Therefore, there exists a difference in construction therebetween.
With reference to
FIG. 10A
, a MOSFET of a logic device comprises a well
2
c
in a semiconductor substrate not shown, a gate electrode
3
c
, a gate insulating film
4
c
and sidewalls
6
which are formed on the well
2
c
, and source/drain diffusion regions
7
c
and
8
c
formed in the well
2
c
. In many cases, the MOSFET of the logic device further comprises regions
11
c
,
12
c
,
13
c
of a compound of metal such as cobalt and silicon, i.e. silicide, which are formed in the surfaces of the gate electrode
3
c
and the source/drain diffusion regions
7
c
,
8
c
since the MOSFET of the logic device which is required to have a high driving capability must reduce the parasitic resistance of an electrode portion by means of the silicidation using metal. Silicidation of the surface of a diffusion region also has the effect of preventing spikes which are prone to occur when a contact interconnect line to the diffusion region is formed.
On the other hand, a MOSFET of a memory device (
FIG. 10B
) is similar to the MOSFET of the logic circuit in that it comprises a gate electrode
3
a
, a gate insulating film
4
a
and sidewalls
6
which are formed on a well
2
a
, and source/drain diffusion regions
7
a
,
8
a
formed in the well
2
a
. The MOSFET of the memory device, however, is constructed such that only the gate electrode
3
a
has a silicided region
23
a
, unlike the MOSFET of the logic device in which each of the electrode portions has a silicided region.
The gate electrode
3
a
is silicided for the above described reasons. The other electrode portions are not silicided to prevent a leakage current which is prone to flow from the source/drain diffusion regions
7
a
,
8
a
to the well
2
a
. A flow of the leakage current causes electric charges to flow out of a storage node of a capacitor connected to one of the source/drain diffusion regions
7
a
and
8
a
, resulting in the decrease in the ability of the capacitor to hold information. Silicidation using metal forms a new energy level in a band gap of silicon to increase the number of carriers in the electrode portions, thereby causing a leakage current to readily flow. For this reason, the source/drain diffusion regions
7
a
and
8
a
are not silicided.
A method of manufacturing MOSFETs of the above-mentioned hybrid logic-memory device is described with reference to
FIGS. 11 through 16
. Two regions in a right half of
FIGS. 11 through 16
are defined as a memory device region as labeled “DRAM” in
FIG. 11
, and two regions in a left half thereof are defined as a logic device region as labeled “LOGIC” in FIG.
11
. The process of formation of both N-type and P-type MOSFETs in each of the memory and logic device regions is illustrated.
Initially, isolation regions
5
are formed on the semiconductor substrate
1
by the LOCOS (LOCal Oxidation of Silicon) process and the like. A photoresist not shown is applied to the surface of the semiconductor substrate
1
and patterned. Using the patterned photoresist as a mask, impurities are implanted into the semiconductor substrate
1
to form the P-type wells
2
a
and
2
c
. Then, the photoresist is removed. likewise, N-type wells
2
b
and
2
d
are formed (FIG.
11
).
Next, the MOSFETs of the memory device are formed. Thermal oxidation of the surface of the wells
2
a
to
2
d
forms gate insulating films
4
a
to
4
d
, respectively. Phosphorus-containing polycrystalline silicon, for example, is deposited on the entire surfaces of the gate insulating films
4
a
to
4
d
and the isolation regions
5
by the low pressure CVD (referred to hereinafter as “LPCVD”) process. Tungsten, for example, is deposited on the phosphorus-containing polycrystalline silicon. Then, heat treatment is performed to form a compound of tungsten and polycrystalline silicon, i.e. tungsten silicide. A silicon oxide film serving as a mask for the patterning of the polycrystalline silicon and tungsten silicide into the form of gate electrodes is deposited by the CVD process. A photoresist is applied and patterned. Using the photoresist as a mask, the silicon oxide film is etched. The photoresist is then removed. This provides patterned silicon oxide films
24
a
and
24
b
. Using the silicon oxide films
24
a
and
24
b
as a mask, etching is performed on the underlying structure to form a gate electrode including polycrystalline silicon
3
a
and tungsten silicide
23
a
and a gate electrode including polycrystalline silicon
3
b
and tungsten silicide
23
b
in the memory device region (FIG.
12
). Such silicided polycrystalline silicon used for a gate electrode is referred to as polycide.
The N-type well
2
b
in the memory device region and the entire logic device region are covered with a photoresist. Phosphorus ions, for example, are implanted into the P-type well
2
a
in the memory device region by the ion implantation technique to form N
−
source/drain diffusion regions
9
a
for use in an LDD (Lightly Doped Drain) structure. Then, the photoresist is removed. Likewise, the P-type well
2
a
and the entire logic device region are covered with a photoresist, and boron ions, for example, are implanted into the N-type well
2
b
to form P
−
source/drain diffusion regions
9
b
for use in the LDD structure.
Then, the photoresist is removed. A silicon oxide film is deposited on the surface of the semiconductor substrate
1
and then etched back to form the sidewalls
6
. Parts of the gate insulating films
4
a
and
4
b
which lie outside the sidewalls
6
are etched away at the same time. Thereafter, the N-type well
2
b
and the entire logic device region are covered again with a photoresist, and phosphorus ions are implanted into the P-type well
2
a
to form the N
+
source/drain diffusion regions
7
a
and
8
a
. Then, the photoresist is removed. The P-type well
2
a
and the entire logic device region are covered again with a photoresist, and boron ions are implanted into the N-type well
2
b
to form P
+
source/drain diffusion regions
7
b
and
8
b
. Then, the photoresist is removed (FIG.
13
).
Prior to the next step of forming the MOSFETs in the logic device region, an oxidation-resistant silicon nitride film
25
is formed to cover the entire memory device region so that oxidation does not proceed in the memory device region (FIG.
14
).
For the formation of the MOSFETs in the logic device region, impurity-free polycrystalline silicon is initially deposited on the entire surface of the semiconductor substrate
1
by the LPCVD process. A photoresist is patterned so that only part of the polycrystalline silicon which overlies the P-type well
2
c
in the logic device region is exposed. Phosphorus ions are implanted into the exposed part of the polycrystalline silicon to form N-type polycrystalline silicon. Then, the photoresist is removed. Likewise, a photoresist is patterned so that only part of the polycrystalline silicon which overlies the N-type well
2
d
is exposed, and boron ions are implanted into the exposed part of the polycrystalline silicon to form P-type polycrystalline

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